This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428

talk to the MCStreamer directly instead.

llvm-svn: 79405

Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).

llvm-svn: 79377

- Drop the Candidates argument and fix all callers. Now that RegScavenger
  tracks available registers accurately, there is no need to restict the
  search.
- Make sure that no aliases of the found register are in use. This was a potential bug.

llvm-svn: 79369

llvm-svn: 79368

llvm-svn: 79351

llvm-svn: 79346

Patch by Dmitry Gorbachev!

llvm-svn: 79334

llvm-svn: 79321

llvm-svn: 79318

send instructions like:

NEW: 	movl	"L___stack_chk_guard$non_lazy_ptr" - "L1$pb"(%esi), %eax
OLD: 	movl	L___stack_chk_guard$non_lazy_ptr-"L1$pb"(%esi), %eax

through the streamer.  Several fixmes.

llvm-svn: 79317

returns a log2 value.

llvm-svn: 79293

for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible.  7144566.

llvm-svn: 79292

Clear the uniquing table when initializing TLOF to avoid a crash when the TLOF is reinitialized with a different MCContext.

llvm-svn: 79253

if not supported by the ELF subtarget.

llvm-svn: 79249

just remove the argument and replace it with 1.

llvm-svn: 79246

or some other situation where no xmm registers need to be saved.

llvm-svn: 79207

llvm-svn: 79206

llvm-svn: 79189

llvm-svn: 79187

llvm-svn: 79175

can asmprint:

NEW: 	movl	"L___stack_chk_guard$non_lazy_ptr", %eax
OLD: 	movl	L___stack_chk_guard$non_lazy_ptr, %eax

where 'new' is coming out of the MCInst version of the printer.

llvm-svn: 79170

llvm-svn: 79167

llvm-svn: 79165

what was there before. In "no FP mode", we weren't generating labels and unwind
table entries after each "push" instruction. While more than likely "okay", it's
not technically correct. The major thing was that the ordering of when to define
a new CFA register and at what offset wasn't correct. This would cause the
exception handling to fail in ways most miserable to users.

I also cleaned up some code a bit. There's one function which has a "return" at
the beginning, so it's never used. Should I just remove it? :-)

llvm-svn: 79139

llvm-svn: 79136

llvm-svn: 79135

support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127

is why they are datarel).  This should fix PR4724, and is fallout
from r78890.

llvm-svn: 79111

llvm-svn: 79107

llvm-svn: 79101

llvm-svn: 79098

PIC16DebugInfo currently rely on NameStr of composite type descriptors to uniquely
identify debug info for two aggregate type decls with same name.
This implementation will change when we have MDNodes based debug info implemenatation in place

llvm-svn: 79097

llvm-svn: 79094

The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.

llvm-svn: 79091

llvm-svn: 79084

llvm-svn: 79082

the class it defines.

llvm-svn: 79081

llvm-svn: 79080

support for globals going into the appropriate sections with the flags.

This hopefully finishes unbreaking the previous behavior that I broke before.

llvm-svn: 79079