instructions.

llvm-svn: 110360

llvm-svn: 110359

Partial fix for PR7792.

llvm-svn: 110358

preserves the existing behavior, as it seems a concious choice to allow RS to
be null and BigStack marked true.

llvm-svn: 110307

llvm-svn: 110292

uses.

llvm-svn: 110274

llvm-svn: 110269

llvm-svn: 110268

llvm-svn: 110267

llvm-svn: 110259

simplify the call frame pseudo instructions. In that situation, the
calculations for estimating the stack size will be way off, leading to
not having an emergency spill slot when we need one. It should be possible
to be more precise about tracking the adjustment values, but not really
necessary for correctness. Upcoming cleanups for PEI in general will
render that moot.

llvm-svn: 110258

llvm-svn: 110256

See PR5201. There is no way to know if direct calls will be within the allowed
range for BL. Hence emit all calls as indirect when in JIT mode.
Without this long-running applications will fail to JIT on PowerPC with a
relocation failure.

llvm-svn: 110246

seem to be working correctly.  No functional change.

llvm-svn: 110226

llvm-svn: 110224

llvm-svn: 110200

store for "half vectors"

llvm-svn: 110198

- The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an
  error, but it's still much better than random assertions from the MachO backend.
- We want to make ELF the default eventually, it's what the majority of targets use.

llvm-svn: 110197

"The CWriter::GetValueName() method does not check if a value as an alias 
and emits the alias name which will never be defined in the output .c 
file (so the output file fails to compile). This can happen if you have 
multiple inheritance with several destructors defined by clang (...D0Ev, 
...D1Ev, ...D2Ev)."

-- applied with minor tweaks. Thanks!

llvm-svn: 110194

(absolute difference with accumulate) intrinsics.  Radar 8228576.

llvm-svn: 110170

llvm-svn: 110164

Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.

llvm-svn: 110152

XCore->XCoreGen
PIC16->PIC16CodeGen

After updating your working copy, the first build will fail because it
is using the old library dependencies. Start the build again and it
will work fine.

llvm-svn: 110127

llvm-svn: 110038

duplicate the instructions and operate on half vectors. 

Also reorder code in SPUInstrInfo.td for better coherency.

llvm-svn: 110037

such registers in SPU, this support boils down to "emulating" 
them by duplicating instructions on the general purpose registers. 

This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.

llvm-svn: 110035

llvm-svn: 109998

improves the generated code in some cases.

llvm-svn: 109985

llvm-svn: 109956

llvm-svn: 109949

the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948

llvm-svn: 109947

llvm-svn: 109946

Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues.

llvm-svn: 109934

reference registers past the end of the NEON register file, and report them
as invalid instead of asserting when trying to print them.  PR7746.

llvm-svn: 109933

formerly rejected by the FE, so asserted in the BE; now the FE only
warns, so we treat it as a legitimate fatal error in PPC BE.
This means the test for the feature won't pass, so it's xfail'd.

llvm-svn: 109892

beginning on ARM Darwin assembly files so that it won't be placed after
debug sections.  Radar 8252813.

llvm-svn: 109879

declared during the addition of the assembler support, the additional
changes are:
- Add missing intrinsics
- Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file.
- Duplicate some patterns to AVX mode.
- Step into PCMPEST/PCMPIST custom inserter and add AVX versions.

llvm-svn: 109878

llvm-svn: 109877

have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
  mls r0,r9,r0,sp
instead of:
  mov r2, sp
  mls r0, r9, r0, r2

This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.

PR7499

llvm-svn: 109842