from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814

X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812

Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32.  This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly.  Fixes PR10802.

llvm-svn: 138768

llvm-svn: 138744

llvm-svn: 138725

llvm-svn: 138723

llvm-svn: 138706

llvm-svn: 138660

llvm-svn: 138623

llvm-svn: 138592

llvm-svn: 138588

llvm-svn: 138587

Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.

llvm-svn: 138553

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138546

llvm-svn: 138545

file, and move more code around!

llvm-svn: 138521

llvm-svn: 138520

llvm-svn: 138519

the missing ones for AVX.

llvm-svn: 138518

llvm-svn: 138517

pattern for 128-bit AVX mode.

llvm-svn: 138516

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!

llvm-svn: 138515

explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!

llvm-svn: 138514

Hook up 64-bit atomic load/store on x86-32.  I plan to write more efficient implementations eventually.

llvm-svn: 138505

llvm-svn: 138487

llvm-svn: 138478

llvm-svn: 138461

These are strictly utilities for registering targets and components.

llvm-svn: 138450

Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.

llvm-svn: 138427

permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392

from MC.

llvm-svn: 138367

llvm-svn: 138354

Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.

llvm-svn: 138321

SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317

llvm-svn: 138285

avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271

llvm-svn: 138270

a bug and add a testcase!

llvm-svn: 138123

llvm-svn: 138034