- Oct 28, 2010
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Jim Grosbach authored
the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
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Owen Anderson authored
llvm-svn: 117502
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Owen Anderson authored
for specifying fractional bits for fixed point conversions. llvm-svn: 117501
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- Oct 27, 2010
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Jim Grosbach authored
llvm-svn: 117496
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Owen Anderson authored
llvm-svn: 117495
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Rafael Espindola authored
llvm-svn: 117494
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Kevin Enderby authored
llvm-svn: 117485
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Jim Grosbach authored
llvm-svn: 117483
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Bob Wilson authored
elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482
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Rafael Espindola authored
llvm-svn: 117481
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Jim Grosbach authored
llvm-svn: 117478
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Benjamin Kramer authored
llvm-svn: 117477
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Owen Anderson authored
llvm-svn: 117475
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Michael J. Spencer authored
llvm-svn: 117474
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Michael J. Spencer authored
There are currently 100 references to COFF::IMAGE_SCN in 6 files and 11 different functions. Section to attribute mapping really needs to happen in one place to avoid problems like this. llvm-svn: 117473
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Michael J. Spencer authored
llvm-svn: 117472
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Rafael Espindola authored
llvm-svn: 117471
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Owen Anderson authored
llvm-svn: 117469
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Devang Patel authored
llvm-svn: 117468
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Owen Anderson authored
llvm-svn: 117466
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Owen Anderson authored
llvm-svn: 117463
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Rafael Espindola authored
llvm-svn: 117462
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Jim Grosbach authored
operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
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Owen Anderson authored
llvm-svn: 117460
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Owen Anderson authored
llvm-svn: 117459
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Owen Anderson authored
llvm-svn: 117458
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Jim Grosbach authored
encoding tricks. Handle the 'imm doesn't fit in the insn' case. llvm-svn: 117454
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Jim Grosbach authored
llvm-svn: 117453
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Rafael Espindola authored
llvm-svn: 117451
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Rafael Espindola authored
contained in the ELF object writer. llvm-svn: 117448
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Rafael Espindola authored
llvm-svn: 117447
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Mikhail Glushenkov authored
llvm-svn: 117443
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Mikhail Glushenkov authored
catch(...) is used in Win32/Signals.inc for catching Win32 structured exceptions, but according to [1], this is wrong. We can't simply change try/catch to __try/__finally, since this syntax is not supported by MinGW. We can use __try/__finally on MSVC and __try1/__except1 macros on MinGW [2], but I think that that solution obfuscates the code too much. The use of try/catch(...) in Signals.inc makes it impossible to link MinGW-compiled libSystem with llvm-gcc compiled executables. I propose that we just remove try/catch(...) from Signals.inc, since the meaning of the code won't change. [1] http://members.cox.net/doug_web/eh.htm [2] http://article.gmane.org/gmane.comp.compilers.llvm.cvs/81315 llvm-svn: 117442
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Mikhail Glushenkov authored
llvm-svn: 117441
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Mikhail Glushenkov authored
llvm-svn: 117440
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Kevin Enderby authored
(still to add ud2b). llvm-svn: 117435
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Kevin Enderby authored
the wait prefix). llvm-svn: 117434
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Kevin Enderby authored
sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. llvm-svn: 117433
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Jim Grosbach authored
integer values), not with the addrmode2 encoding. llvm-svn: 117429
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Bill Wendling authored
llvm-svn: 117428
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