llvm-svn: 107276

llvm-svn: 107275

llvm-svn: 107273

llvm-svn: 107272

llvm-svn: 107271

llvm-svn: 107270

llvm-svn: 107269

llvm-svn: 107257

the old one instead of replacing it, to be more precise.

llvm-svn: 107256

on ScalarEvolution successfully folding and preserving
range information for both A-B and B-A. Now, if it gets
either one, it's sufficient.

llvm-svn: 107249

llvm-svn: 107248

llvm-svn: 107246

llvm-svn: 107245

llvm-svn: 107244

llvm-svn: 107243

llvm-svn: 107241

llvm-svn: 107240

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

llvm-svn: 107237

llvm-svn: 107234

llvm-svn: 107233

Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree. 

llvm-svn: 107228

InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.

This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.

llvm-svn: 107227

llvm-svn: 107225

where each loop's induction variable's start value is the exit
value of a preceding loop.

llvm-svn: 107224

llvm-svn: 107215

llvm-svn: 107214

llvm-svn: 107213

llvm-svn: 107211

llvm-svn: 107208

llvm-svn: 107206

metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

llvm-svn: 107205

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

Inspired by Artur Pietrek.

llvm-svn: 107202

llvm-svn: 107201

A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.

This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.

llvm-svn: 107193

The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.

llvm-svn: 107189

llvm-svn: 107178

llvm-svn: 107175

llvm-svn: 107168