generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

Patch by Sanjoy Das!

llvm-svn: 133910

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155

Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044

Get rid of static constructors for pass registration.  Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820

llvm-svn: 115996

Reserved registers are unpredictable, and are treated as always live by machine
DCE.

Allocatable registers are never reserved, and can be used for virtual registers.

Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.

llvm-svn: 112649

llvm-svn: 110460

llvm-svn: 110410

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

llvm-svn: 109045

llvm-svn: 97578

didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.

llvm-svn: 95996

same dead instruction.

llvm-svn: 95890

legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816

llvm-svn: 95736

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493

let that stop it from being deleted, and change the
DEBUG_VALUE value to undef.

llvm-svn: 94694

Change errs() to dbgs().

llvm-svn: 92496

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687

llvm-svn: 79748

llvm-svn: 78663

llvm-svn: 57618

computation. A def of a register doesn't necessarily kill
live super-registers.

llvm-svn: 57614

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56602

separate method.

llvm-svn: 56531

dead loads.

llvm-svn: 56529

correctly, it's not necessary to explicitly remove registers
from their use-def lists.

llvm-svn: 56509

efficient implementation possible, but it's pretty simple and
good enough for the time being.

llvm-svn: 56504

defs to be necessarily live.

llvm-svn: 56310

be used with fast-isel.

llvm-svn: 56268