There's no need to add additional predicate operands when converting a tB to a tBfar now.  Fixes nightly test failures on armv6 Thumb.  <rdar://problem/10110404>

llvm-svn: 139531

llvm-svn: 139530

However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528

llvm-svn: 139527

llvm-svn: 139526

llvm-svn: 139525

Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

llvm-svn: 139522

llvm-svn: 139518

llvm-svn: 139517

llvm-svn: 139515

llvm-svn: 139505

llvm-svn: 139504

llvm-svn: 139503

It has been enabled by default for a while, it was only there to allow
performance comparisons.

llvm-svn: 139501

SplitKit always computes a complement live range to cover the places
where the original live range was live, but no explicit region has been
allocated.

Currently, the complement live range is created to be as small as
possible - it never overlaps any of the regions.  This minimizes
register pressure, but if the complement is going to be spilled anyway,
that is not very important.  The spiller will eliminate redundant
spills, and hoist others by making the spill slot live range overlap
some of the regions created by splitting.  Stack slots are cheap.

This patch adds the interface to enable spill modes in SplitKit.  In
spill mode, SplitKit will assume that the complement is going to spill,
so it will allow it to overlap regions in order to avoid back-copies.
By doing some of the spiller's work early, the complement live range
becomes simpler.  In some cases, it can become much simpler because no
extra PHI-defs are required.  This will speed up both splitting and
spilling.

This is only the interface to enable spill modes, no implementation yet.

llvm-svn: 139500

llvm-svn: 139498

This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495

llvm-svn: 139494

llvm-svn: 139491

Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

llvm-svn: 139486

llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

llvm-svn: 139481

llvm-svn: 139480

Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.

llvm-svn: 139479

llvm-svn: 139459

r139454 activates an assert in a case where we were doing the right thing anyway.  Make that explicit, and un-XFAIL the testcase.

llvm-svn: 139458

lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139456

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454

better.

Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.

llvm-svn: 139453

such.

I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.

llvm-svn: 139450

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139449

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433

llvm-svn: 139432

llvm-svn: 139431

llvm-svn: 139429

llvm-svn: 139422

llvm-svn: 139421

llvm-svn: 139420