llvm-svn: 25004

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

llvm-svn: 24990

llvm-svn: 24979

llvm-svn: 24935

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921

llvm-svn: 24920

llvm-svn: 24919

bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917

llvm-svn: 24900

that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899

llvm-svn: 24898

llvm-svn: 24889

  for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888

llvm-svn: 24886

llvm-svn: 24879

llvm-svn: 24877

llvm-svn: 24870

llvm-svn: 24867

llvm-svn: 24781

llvm-svn: 24775

llvm-svn: 24768

llvm-svn: 24763

llvm-svn: 24760

llvm-svn: 24759

llvm-svn: 24757

llvm-svn: 24756

llvm-svn: 24755

llvm-svn: 24754

llvm-svn: 24727

* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726

leaaddr.

llvm-svn: 24724

llvm-svn: 24722

llvm-svn: 24721

llvm-svn: 24717

llvm-svn: 24705

llvm-svn: 24696

llvm-svn: 24695

llvm-svn: 24693

llvm-svn: 24690