llvm-svn: 48047

it tries to initialize them.

llvm-svn: 48046

llvm-svn: 48044

are looking pretty good now.

llvm-svn: 48043

Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.

llvm-svn: 48042

llvm-svn: 48041

kills the sub-register.

llvm-svn: 48038

llvm-svn: 48035

by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030

llvm-svn: 48029

but there are bugs.

llvm-svn: 48028

llvm-svn: 48027

with 32 or 64-bit operands/results.

llvm-svn: 48026

Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.

llvm-svn: 48024

llvm-svn: 48020

llvm-svn: 48019

add a pass that can extract all kinds of global values, not just functions.  Update llvm-extract to use it and optionally extract a global variable if you want it too

llvm-svn: 48015

llvm-svn: 48010

No functionality change.

llvm-svn: 48009

we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006

    %r3<def> = OR %x3<kill>, %x3

We don't want to mark the %r3 as unused even though it's a sub-register of %x3.

llvm-svn: 48003

llvm-svn: 47998

llvm-svn: 47996

llvm-svn: 47994

llvm-svn: 47992

under modulo (overflow). Fixes PR1933.

llvm-svn: 47987

upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985

llvm-svn: 47981

llvm-svn: 47980

correct now.

llvm-svn: 47978

llvm-svn: 47977

llvm-svn: 47975

llvm-svn: 47974

  using IL, ILA, et. al. v2i64 and i64 are now supported by
  the select bits (SELB) instruction.

- Add missing comparison operations (testcase forthcoming)

- More multiclass refactoring.

llvm-svn: 47973

llvm-svn: 47968

llvm-svn: 47966

llvm-svn: 47965

Patch by Curtis Dunham.

llvm-svn: 47959

and add some protection against creating such.

llvm-svn: 47957

llvm-svn: 47948