llvm-svn: 123389

Patch by arrowdodger!

llvm-svn: 123388

set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

llvm-svn: 123387

It will still return an iterator that points to the first terminator or end(),
but there may be DBG_VALUE instructions following the first terminator.

llvm-svn: 123384

llvm-svn: 123383

This is a minor extension of SROA to handle a special case that is
important for some ARM NEON operations.  Some of the NEON intrinsics
return multiple values, which are handled as struct types containing
multiple elements of the same vector type.  The corresponding return
types declared in the arm_neon.h header have equivalent arrays.  We
need SROA to recognize that it can split up those arrays and structs
into separate vectors, even though they are not always accessed with
the same type.  SROA already handles loads and stores of an entire
alloca by using insertvalue/extractvalue to access the individual
pieces, and that code works the same regardless of whether the type
is a struct or an array.  So, all that needs to be done is to check
for compatible arrays and homogeneous structs.

llvm-svn: 123381

SROA only split up structs and arrays one level at a time, so padding can
only cause trouble if it is located in between the struct or array elements.

llvm-svn: 123380

llvm-svn: 123377

Patch by arrowdodger!

llvm-svn: 123376

the comment I added): an extern weak global may have a null address.

llvm-svn: 123373

is "X != 0 -> X" when X is a boolean.  This occurs a lot because of the way
llvm-gcc converts gcc's conditional expressions.  Add this, and a few other
similar transforms for completeness.

llvm-svn: 123372

in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369

16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367

llvm-svn: 123364

llvm-svn: 123358

.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.

llvm-svn: 123353

llvm-svn: 123352

llvm-svn: 123351

llvm-svn: 123350

llvm-svn: 123347

further on the associated testcase before aborting.

llvm-svn: 123346

llvm-svn: 123345

llvm-svn: 123342

llvm-svn: 123341

that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340

llvm-svn: 123339

llvm-svn: 123338

Make sure we don't crash in that case, but simply turn them into %noreg instead.

llvm-svn: 123335

It was leaving dangling pointers in the slot index maps.

llvm-svn: 123334

llvm-svn: 123333

The slot indexes must be monotonically increasing through the function.

llvm-svn: 123324

llvm-svn: 123323

llvm-svn: 123322

enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321

llvm-svn: 123318

of the switch block to appease GCC.

llvm-svn: 123317

llvm-svn: 123315

llvm-svn: 123310

ensure %o7 is not assigned as the destination of getpcx instruction.

llvm-svn: 123304

llvm-svn: 123302