memoizing code when IV's are used by phinodes outside of loops.  In a simple
example, we were getting this code before (note that r6 and r7 are isomorphic
IV's):

        li r6, 0
        or r7, r6, r6
LBB_test_3:     ; no_exit
        lwz r2, 0(r3)
        cmpw cr0, r2, r5
        or r2, r7, r7
        beq cr0, LBB_test_5     ; loopexit
LBB_test_4:     ; endif
        addi r2, r7, 1
        addi r7, r7, 1
        addi r3, r3, 4
        addi r6, r6, 1
        cmpw cr0, r6, r4
        blt cr0, LBB_test_3     ; no_exit

Now we get:

        li r6, 0
LBB_test_3:     ; no_exit
        or r2, r6, r6
        lwz r6, 0(r3)
        cmpw cr0, r6, r5
        beq cr0, LBB_test_6     ; loopexit
LBB_test_4:     ; endif
        addi r3, r3, 4
        addi r6, r2, 1
        cmpw cr0, r6, r4
        blt cr0, LBB_test_3     ; no_exit

this was noticed in em3d.

llvm-svn: 23602

check the presplit pred, not the post-split pred.  This was causing us
to make the wrong decision in some cases, leaving the critical edge block
in the loop.

llvm-svn: 23601

llvm-svn: 23600

llvm-svn: 23599

large basic blocks because it was purely recursive.  This switches it to an
iterative/recursive hybrid.

llvm-svn: 23596

llvm-svn: 23595

llvm-svn: 23594

llvm-svn: 23593

llvm-svn: 23592

compile with an assertion that the tables are not sorted!

llvm-svn: 23591

up between defs and uses.

llvm-svn: 23590

the comparison to be 64-bits.  This is fine because extensions from float
to double are free.

llvm-svn: 23589

split the FSEL family into 4 things instead of just two.

llvm-svn: 23588

llvm-svn: 23587

destination vreg.

llvm-svn: 23586

llvm-svn: 23585

llvm-svn: 23584

llvm-svn: 23583

we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.

llvm-svn: 23582

llvm-svn: 23581

For instructions that define multiple results, use the right regclass
to define the result, not always the rc of result #0

llvm-svn: 23580

llvm-svn: 23579

llvm-svn: 23578

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577

This is Jim's feature implemented so that graphs could 'opt-in' and get
this behavior.  This is currently used by selection dags.

llvm-svn: 23576

llvm-svn: 23575

llvm-svn: 23574

2. Printing node groups when displaying nodes.

llvm-svn: 23573

llvm-svn: 23572

llvm-svn: 23571

llvm-svn: 23570

llvm-svn: 23569

llvm-svn: 23568

llvm-svn: 23567

2. Added node groups to handle flagged nodes.

3. Started weaning simple scheduling off existing emitter.

llvm-svn: 23566

llvm-svn: 23565

llvm-svn: 23564

llvm-svn: 23563

llvm-svn: 23562

trim down the target info structs now that we have a preferred spill register class for each callee save register

Why is V9 maintaining these tables manually? ugh!

llvm-svn: 23561