transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226

Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224

llvm-svn: 26197

llvm-svn: 26196

llvm-svn: 26193

llvm-svn: 26192

llvm-svn: 26186

llvm-svn: 26183

XMM registers were not being handled.

llvm-svn: 26182

llvm-svn: 26180

llvm-svn: 26179

llvm-svn: 26174

llvm-svn: 26173

maxStoresPerMemMove. Although the last one is not used.

llvm-svn: 26172

llvm-svn: 26169

CALLSEQ_START nodes.

llvm-svn: 26143

X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117

llvm-svn: 26111

llvm-svn: 26110

llvm-svn: 26105

llvm-svn: 26096

llvm-svn: 26085

llvm-svn: 26069

SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067

llvm-svn: 26066

llvm-svn: 26062

llvm-svn: 26054

llvm-svn: 26052

llvm-svn: 26044

specified in bytes.

llvm-svn: 26043

Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.

llvm-svn: 26038

llvm-svn: 26037

printOperand instead.

llvm-svn: 26025

- Manually select SDOperand's returned by TryFoldLoad which make up the
  load address.

llvm-svn: 26012

llvm-svn: 25997

llvm-svn: 25983

llvm-svn: 25980

tblgen patch reverted.

llvm-svn: 25971

Select them afterwards if it returns true.

llvm-svn: 25968

llvm-svn: 25954