Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.

llvm-svn: 106481

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

llvm-svn: 106430

llvm-svn: 106399

llvm-svn: 106382

llvm-svn: 106381

llvm-svn: 106373

Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.

llvm-svn: 106368

llvm-svn: 106362

llvm-svn: 106360

llvm-svn: 106355

llvm-svn: 106348

llvm-svn: 106347

- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344

llvm-svn: 106342

llvm-svn: 106336

(as suggested in radar 8104405).

llvm-svn: 106318

llvm-svn: 106314

limit on the offset that can be materialized without using the register
scavenger.

llvm-svn: 106312

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.

llvm-svn: 106299

MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296

Not turning them on yet.

llvm-svn: 106295

does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289

llvm-svn: 106279

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

llvm-svn: 106204

previously would result in 'cannot yet select' errors.

llvm-svn: 106199

llvm-svn: 106173

This is before LiveVariables anyway, where these kill flags are recalculated.

llvm-svn: 106157

now, so there's no need to disable them.

llvm-svn: 106155

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

llvm-svn: 106058

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

llvm-svn: 106030

llvm-svn: 105994

llvm-svn: 105990

the combined load/store instruction. rdar://7797940

llvm-svn: 105982

immediate" operands.  These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands.  No functional changes.

llvm-svn: 105969

i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.

llvm-svn: 105845