llvm-svn: 106482

Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms

llvm-svn: 106437

Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed

llvm-svn: 106436

Based on a patch by Patrick Marlier!

llvm-svn: 106433

I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

llvm-svn: 106413

llvm-svn: 106408

llvm-svn: 106405

llvm-svn: 106375

AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374

llvm-svn: 106372

llvm-svn: 106371

llvm-svn: 106370

and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

llvm-svn: 106367

llvm-svn: 106366

llvm-svn: 106365

segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364

llvm-svn: 106361

llvm-svn: 106359

llvm-svn: 106358

llvm-svn: 106357

llvm-svn: 106356

on calls and similar instructions.

llvm-svn: 106353

llvm-svn: 106349

llvm-svn: 106327

llvm-svn: 106311

original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.

llvm-svn: 106310

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

llvm-svn: 106273

to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266

llvm-svn: 106264

which is faster, simpler, and less surprising.

llvm-svn: 106263

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.

llvm-svn: 106049