llvm-svn: 31774

Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).

llvm-svn: 31770

addrmodes.

llvm-svn: 31757

pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.

llvm-svn: 31749

llvm-svn: 31736

clobber.  This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity.  This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.

llvm-svn: 31734

globals.

llvm-svn: 31672

llvm-svn: 31637

(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621

llvm-svn: 31535

llvm-svn: 31450

that takes a register and condition code.  Print these pieces of BLR the
right way, even though it is currently set to 'always'.

Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.

llvm-svn: 31449

llvm-svn: 31438

llvm-svn: 31433

llvm-svn: 31148

llvm-svn: 30945

llvm-svn: 30936

llvm-svn: 30908

llvm-svn: 30891

llvm-svn: 30844

llvm-svn: 30621

llvm-svn: 30577

llvm-svn: 29603

As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208

llvm-svn: 29174

into i16/i32 load/stores.

llvm-svn: 29089

llvm-svn: 28931

llvm-svn: 28929

doesn't work right).

llvm-svn: 28921

llvm-svn: 28918

llvm-svn: 28917

llvm-svn: 28890

llvm-svn: 28889

llvm-svn: 28888

llvm-svn: 28886

Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883

llvm-svn: 28880

removed, tblgen produces identical output to with them in.

llvm-svn: 28867

llvm-svn: 28840

now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839