Not turning them on yet.

llvm-svn: 106295

so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.

This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block.  Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable.  That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.

This is pretty fragile.  If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion.  But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.

Evan, please review!

llvm-svn: 106291

does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289

llvm-svn: 106287

llvm-svn: 106286

switch from this:

  if (TimePassesIsEnabled) {
    NamedRegionTimer T(Name, GroupName);
    do_something();
  } else {
    do_something(); // duplicate the code, this time without a timer!
  }

to this:

  {
    NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
    do_something();
  }

llvm-svn: 106285

the old one.

llvm-svn: 106284

Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.

llvm-svn: 106283

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

is more consistent with the ConstantInt API.

llvm-svn: 106281

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

llvm-svn: 106273

Fix from Russel Power in PR7284.

llvm-svn: 106271

This fixes PR7333.

llvm-svn: 106267

to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266

llvm-svn: 106264

which is faster, simpler, and less surprising.

llvm-svn: 106263

llvm-svn: 106260

llvm-svn: 106256

llvm-svn: 106254

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

for correctness' sake, it should be there.

llvm-svn: 106229

for the moment. The implementation of the libcall will follow.

Currently, the llvm-gcc knows when the intrinsics can be correctly handled by
the back end and only generates them in those cases, issuing libcalls directly
otherwise. That's too much coupling. The intrinsics should always be
generated and the back end decide how to handle them, be it with a libcall,
inline code, or whatever. This patch is a step in that direction.

rdar://8097623

llvm-svn: 106227

ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

llvm-svn: 106204

sets the legalize action to Expand.

llvm-svn: 106203

previously would result in 'cannot yet select' errors.

llvm-svn: 106199

DW_OP_breg[0..31] to Dwarf.h.

Add "DW_" prefix to the llvm::dwarf::*String methods which did not
already have them in Dwarf.cpp.

llvm-svn: 106197

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

llvm-svn: 106191

llvm-svn: 106173

llvm-svn: 106164

This is before LiveVariables anyway, where these kill flags are recalculated.

llvm-svn: 106157

now, so there's no need to disable them.

llvm-svn: 106155

llvm-svn: 106154

LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

llvm-svn: 106152

when iterating through instructions. Yet more work for rdar://7797940

llvm-svn: 106149

MC/Mach-O: Rewrite atom association to be a final pass we do in Finish(), instead of tracking as part of emission.
 - This allows sharing more code with the MCObjectStreamer.

llvm-svn: 106143