Commits · 3b775b8cc34365fdf9ace8ab45dd0539ddf0771d · Roger Ferrer / llvm-epi-0.8

Jan 04, 2012

Rename immLUiOpnd. · 3b775b8c
Akira Hatanaka authored Jan 04, 2012
```
llvm-svn: 147519
```
3b775b8c

- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit · b89a4bfe

Akira Hatanaka authored Jan 04, 2012

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

b89a4bfe

Dec 24, 2011
- If target ABI is N64, LEA should be daddiu. · 695d113a
  Akira Hatanaka authored Dec 24, 2011
```
llvm-svn: 147232
```
  695d113a
Dec 21, 2011

Add definition of DSBH (Double Swap Bytes within Halfwords) and · 4706ac97

Akira Hatanaka authored Dec 20, 2011

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

4706ac97

Dec 20, 2011
- 32-to-64-bit sext_inreg pattern. · 494fdf14
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147004
```
  494fdf14
- Add 64-bit extload patterns. · 8756816e
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 147003
```
  8756816e
- 32-to-64-bit sign extension pattern. · 4e210691
  Akira Hatanaka authored Dec 20, 2011
```
llvm-svn: 146995
```
  4e210691
Dec 19, 2011
- Add patterns for matching immediates whose lower 16-bit is cleared. These · db47e0c4
  Akira Hatanaka authored Dec 19, 2011
```
patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900
```
  db47e0c4
- Remove definitions of double word shift plus 32 instructions. Assembler or · 2a232d81
  Akira Hatanaka authored Dec 19, 2011
```
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893
```
  2a232d81
- Remove unused predicate. · c4db30e3
  Akira Hatanaka authored Dec 19, 2011
```
llvm-svn: 146889
```
  c4db30e3
Dec 09, 2011
- Rename WrapperPIC. It is now used for both pic and static. · 5ee8464e
  Akira Hatanaka authored Dec 09, 2011
```
llvm-svn: 146232
```
  5ee8464e
Dec 08, 2011
- Implement 64-bit support for thread local storage handling. · dee6c827
  Akira Hatanaka authored Dec 08, 2011
```
- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175
```
  dee6c827
- Modify class ReadHardware and add definition of 64-bit version of instruction · 4350c183
  Akira Hatanaka authored Dec 07, 2011
```
RDHWR. 

llvm-svn: 146101
```
  4350c183
- 32 to 64-bit anyext pattern. · 9778e7a6
  Akira Hatanaka authored Dec 07, 2011
```
llvm-svn: 146097
```
  9778e7a6
- 32 to 64-bit zext pattern. · ae378af6
  Akira Hatanaka authored Dec 07, 2011
```
llvm-svn: 146096
```
  ae378af6
Dec 07, 2011
- 64-bit WrapperPICPat patterns. · b2e05cb6
  Akira Hatanaka authored Dec 07, 2011
```
llvm-svn: 146086
```
  b2e05cb6
- Fix 64-bit immediate patterns. · 4a04a56a
  Akira Hatanaka authored Dec 07, 2011
```
llvm-svn: 146059
```
  4a04a56a
Dec 05, 2011
- Add definitions of 64-bit extract and insert instrucions and make · 20cee2eb
  Akira Hatanaka authored Dec 05, 2011
```
PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853
```
  20cee2eb
Nov 16, 2011
- Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool · 7b8547c4
  Akira Hatanaka authored Nov 16, 2011
```
nodes.

llvm-svn: 144841
```
  7b8547c4
- 64-bit jump register instruction. · 6d617cec
  Akira Hatanaka authored Nov 16, 2011
```
llvm-svn: 144840
```
  6d617cec
Nov 14, 2011
- 32-to-64-bit extended load. · f93b3f46
  Akira Hatanaka authored Nov 14, 2011
```
llvm-svn: 144554
```
  f93b3f46
Nov 12, 2011
- 64-bit arbitrary immediate pattern. · 5ed07c03
  Akira Hatanaka authored Nov 12, 2011
```
llvm-svn: 144448
```
  5ed07c03
Nov 11, 2011
- 64-bit atomic instructions. · 21cbc25b
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144372
```
  21cbc25b
- Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. · 4bdfec57
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144370
```
  4bdfec57
- 64-bit versions of jal, jalr and bal. · 0009dc20
  Akira Hatanaka authored Nov 11, 2011
```
llvm-svn: 144368
```
  0009dc20
Nov 07, 2011
- Add definition of 64-bit load upper immediate. · 2b8d1f16
  Akira Hatanaka authored Nov 07, 2011
```
llvm-svn: 143994
```
  2b8d1f16
- Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted · cf7e5b09
  Akira Hatanaka authored Nov 07, 2011
```
when shift amount is larger than 32.

llvm-svn: 143990
```
  cf7e5b09
- Make the type of shift amount i32 in order to reduce the number of shift · 770f0646
  Akira Hatanaka authored Nov 07, 2011
```
instruction definitions.

llvm-svn: 143989
```
  770f0646
- Add 64-bit to 32-bit trunc pattern. · d5c13290
  Akira Hatanaka authored Nov 07, 2011
```
llvm-svn: 143988
```
  d5c13290
Oct 17, 2011
- Redefine count-leading 0s and 1s instructions. · 33fe8f90
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142216
```
  33fe8f90
- Redefine mfhi/lo and mthi/lo instructions. · 8c446be2
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142214
```
  8c446be2
- Redefine multiply and divide instructions. · 0317b653
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142211
```
  0317b653
- Add definition of a base class for logical shift/rotate instructions with two · 2736bbc0
  Akira Hatanaka authored Oct 17, 2011
```
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
```
  2736bbc0
- Add definition of a base class for logical shift/rotate immediate instructions · 73081309
  Akira Hatanaka authored Oct 17, 2011
```
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
```
  73081309
- Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. · e3f27b79
  Akira Hatanaka authored Oct 17, 2011
```
llvm-svn: 142205
```
  e3f27b79
Oct 12, 2011
- Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. · 3261c0fa
  Akira Hatanaka authored Oct 12, 2011
```
llvm-svn: 141761
```
  3261c0fa
- Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical · 8f0d549c
  Akira Hatanaka authored Oct 11, 2011
```
instructions with two register operands derive from it.

llvm-svn: 141742
```
  8f0d549c
- Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit · ae5a9d65
  Akira Hatanaka authored Oct 11, 2011
```
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
```
  ae5a9d65
Oct 11, 2011
- Change the names of 64-bit logical instructions so that they match the names of · 453ac88b
  Akira Hatanaka authored Oct 11, 2011
```
the real instructions.

llvm-svn: 141718
```
  453ac88b
- Remove redundancy in setcc patterns using multiclass. · 46a7994a
  Akira Hatanaka authored Oct 11, 2011
```
llvm-svn: 141715
```
  46a7994a