This exposes a -segmented-stacks bug.

llvm-svn: 140429

PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.

llvm-svn: 140428

llvm-svn: 140426

Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425

llvm-svn: 140422

Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

llvm-svn: 140420

llvm-svn: 140415

llvm-svn: 140413

llvm-svn: 140412

llvm-svn: 140401

llvm-svn: 140397

callee-saved registers and reserved registers.

llvm-svn: 140395

llvm-svn: 140394

patch contributed by Jia Liu!

llvm-svn: 140391

llvm-svn: 140390

llvm-svn: 140387

llvm-svn: 140386

Original patch by Liu.

llvm-svn: 140385

hadd/hsub intrinsics into the new fhadd/fhsub X86 node.

llvm-svn: 140383

llvm-svn: 140378

llvm-svn: 140377

From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
 lib/Target/PTX/PTXInstrInfo.td          |  165 ++++++++++++++++++++----------
 lib/Target/PTX/PTXIntrinsicInstrInfo.td |   88 +++++++++++------
 2 files changed, 167 insertions(+), 86 deletions(-)

llvm-svn: 140376

llvm-svn: 140375

llvm-svn: 140374

DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).

llvm-svn: 140373

integer-promotion of CONCAT_VECTORS.

Test: test/CodeGen/X86/widen_shuffle-1.ll

This patch fixes the above tests (when running in with -promote-elements).

llvm-svn: 140372

llvm-svn: 140366

Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363

llvm-svn: 140356

PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage.  (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)

llvm-svn: 140355

complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354

llvm-svn: 140352

worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349

We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348

llvm-svn: 140347

Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
These are very much a work in progress, and not really useful yet.

llvm-svn: 140345

Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340

The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339

floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332

llvm-svn: 140327