per compile unit/skeleton compile unit. Update tests accordingly.

llvm-svn: 171133

llvm-svn: 171130

Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.

llvm-svn: 171128

information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.

llvm-svn: 171126

If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified.

PR14719.

llvm-svn: 171124

Fix operands and encoding form for ARPL instruction. Register form had  and  reversed. Memory form writes memory, but was marked as MRMSrcMem.

llvm-svn: 171123

llvm-svn: 171122

llvm-svn: 171121

llvm-svn: 171120

such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.

llvm-svn: 171119

Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.

llvm-svn: 171118

Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.

llvm-svn: 171117

LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1

llvm-svn: 171114

Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.

llvm-svn: 171110

llvm-svn: 171109

llvm-svn: 171103

llvm-svn: 171102

llvm-svn: 171097

llvm-svn: 171096

llvm-svn: 171095

llvm-svn: 171093

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.

llvm-svn: 171092

llvm-svn: 171091

Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN

llvm-svn: 171087

llvm-svn: 171086

llvm-svn: 171085

llvm-svn: 171082

Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...

llvm-svn: 171081

Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.

llvm-svn: 171080

For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.

Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.

llvm-svn: 171079

Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.

llvm-svn: 171078

llvm-svn: 171076

llvm-svn: 171075

Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

llvm-svn: 171072

VectorType::getInteger() can not be used with them, because pointer size
depends on the target.

llvm-svn: 171070

llvm-svn: 171069

llvm-svn: 171064

pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

llvm-svn: 171063

llvm-svn: 171061

llvm-svn: 171060