There were some that might even matter in X86FastISel.

llvm-svn: 64437

leaving them in the DAG and then getting selection errors.  This is a 
fix for PR3538.

llvm-svn: 64382

No functional change.

llvm-svn: 64026

llvm-svn: 63989

its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904

llvm-svn: 63693

llvm-svn: 63664

instead of via a by-reference argument. No functionality change.

llvm-svn: 63118

llvm-svn: 63088

Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.

llvm-svn: 63022

we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691

DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.

llvm-svn: 62519

llvm-svn: 62413

and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275

llvm-svn: 62024

llvm-svn: 60850

On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
e.g.
movl 4(%esp), %eax
addl $4, %eax

is 2 bytes shorter than

movl $4, %eax
addl 4(%esp), %eax

llvm-svn: 60139

special-purpose hook to a new pass. Also, add check to see if any
x87 virtual registers are used, to avoid doing any work in the
common case that no x87 code is needed.

llvm-svn: 59190

to be sign-extended when it is promoted to 64 bits for intermediate
offset calculations. The offset calculations are done as uint64_t so that
overflow conditions are well defined.

This fixes a problem which is currently hidden by the x86 AsmPrinter but
which was exposed by r58917 (which is temporarily reverted).  See PR3027
for details.

llvm-svn: 59044

priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748

have its node id set. The new and and shift nodes are the nodes that need
the IDs. This fixes PR2982.

llvm-svn: 58655

Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278

and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

llvm-svn: 57649

llvm-svn: 57508

create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.

If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.

This fixes PR2849.

llvm-svn: 57465

optimized for size. Set OptForSize for each function separately.

llvm-svn: 57182

Make it all work in non-pic mode.

llvm-svn: 57034

incidentally making the case where the memop is a
pointer deref work.  Fix cmp-and-swap regression.

llvm-svn: 57027

Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016

llvm-svn: 57014

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56963

llvm-svn: 56937

Completely eliminate the TopOrder std::vector. Instead, sort
the AllNodes list in place. This also eliminates the need to
call AllNodes.size(), a linear-time operation, before
performing the sort.

Also, eliminate the Sources temporary std::vector, since it
essentially duplicates the sorted result as it is being
built.

This also changes the direction of the topological sort
from bottom-up to top-down. The AllNodes list starts out in
roughly top-down order, so this reduces the amount of
reordering needed. Top-down is also more convenient for
Legalize, and ISel needed only minor adjustments.

llvm-svn: 56867

and X86FastISel.cpp into X86MachineFunction.h, so that it
can be shared, instead of having each selector keep track
of its own.

llvm-svn: 56825

llvm-svn: 56727

Implement "punpckldq  %xmm0, $xmm0" as "pshufd  $0x50, %xmm0, %xmm" unless optimizing for code size.

llvm-svn: 56711

consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.

llvm-svn: 56700

require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.

llvm-svn: 56676