The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

Test cases for this code are coming. It is not used for anything yet.

llvm-svn: 156327

llvm-svn: 156324

Teach reassociate to commute FMul's and FAdd's in order to canonicalize the order of their operands across instructions.  This allows for greater CSE opportunities.

llvm-svn: 156323

optional library support to the llvm-build tool:
 - Add new command line parameter to llvm-build: “--enable-optional-libraries”
 - Add handing of new llvm-build library type “OptionalLibrary”
 - Update Cmake and automake build systems to pass correct flags to llvm-build
   based on configuration

Patch by Dan Malea!

llvm-svn: 156319

This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

llvm-svn: 156317

single use.
rdar://11360370

llvm-svn: 156316

Fixes a -Woverflow warning from gcc when building for 32-bit platforms.

llvm-svn: 156313

This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709
llvm-svn: 156312

Patch by Jack Carter.

llvm-svn: 156295

Patch by Jack Carter.

llvm-svn: 156294

Patch by Jack Carter.

llvm-svn: 156293

Patch by Jack Carter.

llvm-svn: 156292

llvm-svn: 156287

Patch by Jack Carter.

llvm-svn: 156285

Patch by Jack Carter.

llvm-svn: 156284

Patch by Jack Carter.

llvm-svn: 156283

llvm-svn: 156282

llvm-svn: 156281

Patch by Jack Carter.

llvm-svn: 156280

from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279

Patch by Jack Carter.

llvm-svn: 156278

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277

Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.

llvm-svn: 156268

Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.

llvm-svn: 156266

llvm-svn: 156265

llvm-svn: 156260

The primitive conservative heuristic seems to give a slight overall
improvement while not regressing stuff. Make it available to wider
testing. If you notice any speed regressions (or significant code
size regressions) let me know!

llvm-svn: 156258

llvm-svn: 156257

llvm-svn: 156252

FIXME: GetRandomNumber() is not implemented in Win32.
llvm-svn: 156251

of work for a drive-by fix :)

llvm-svn: 156246

llvm-svn: 156245

refactor some code to expose column numbers more and make diagnostic printing slightly more efficient.

llvm-svn: 156243

llvm-svn: 156241

llvm-svn: 156240

llvm-svn: 156239

 - Just use sys::Process::GetRandomNumber instead of having two poor
   implementations.
 - This is ~70 times (!) faster on my OS X machine.

llvm-svn: 156238

 - Primitive API, but we rarely have need for random numbers.

llvm-svn: 156237

This came up when a change in block placement formed a cmov and slowed down a
hot loop by 50%:

	ucomisd	(%rdi), %xmm0
	cmovbel	%edx, %esi

cmov is a really bad choice in this context because it doesn't get branch
prediction. If we emit it as a branch, an out-of-order CPU can do a better job
(if the branch is predicted right) and avoid waiting for the slow load+compare
instruction to finish. Of course it won't help if the branch is unpredictable,
but those are really rare in practice.

This patch uses a dumb conservative heuristic, it turns all cmovs that have one
use and a direct memory operand into branches. cmovs usually save some code
size, so we disable the transform in -Os mode. In-Order architectures are
unlikely to benefit as well, those are included in the
"predictableSelectIsExpensive" flag.

It would be better to reuse branch probability info here, but BPI doesn't
support select instructions currently. It would make sense to use the same
heuristics as the if-converter pass, which does the opposite direction of this
transform.


Test suite shows a small improvement here and there on corei7-level machines,
but the actual results depend a lot on the used microarchitecture. The
transformation is currently disabled by default and available by passing the
-enable-cgp-select2branch flag to the code generator.

Thanks to Chandler for the initial test case to him and Evan Cheng for providing
me with comments and test-suite numbers that were more stable than mine :)

llvm-svn: 156234