the abbreviations. Part of implementing split dwarf.

llvm-svn: 170589

Use the version that also takes an MF reference instead.

It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.

Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.

llvm-svn: 170588

I introduced it in r166785. PR14291.

If TD is unavailable use getScalarSizeInBits, but don't optimize
pointers or vectors of pointers.

llvm-svn: 170586

 ((x & 0xff00) >> 8) << 2
to
 (x >> 6) & 0x3fc

This is general goodness since it folds a left shift into the mask. However,
the trailing zeros in the mask prevents the ARM backend from using the bit
extraction instructions. And worse since the mask materialization may require
an addition instruction. This comes up fairly frequently when the result of 
the bit twiddling is used as memory address. e.g.

 = ptr[(x & 0xFF0000) >> 16]

We want to generate:
  ubfx   r3, r1, #16, #8
  ldr.w  r3, [r0, r3, lsl #2]

vs.
  mov.w  r9, #1020
  and.w  r2, r9, r1, lsr #14
  ldr    r2, [r0, r2]

Add a late ARM specific isel optimization to
ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the
'base + offset' address computation; change the mask to one which doesn't have
trailing zeros and enable the use of ubfx.

Note the optimization has to be done late since it's target specific and we
don't want to change the DAG normalization. It's also fairly restrictive
as shifter operands are not always free. It's only done for lsh 1 / 2. It's
known to be free on some cpus and they are most common for address
computation.

This is a slight win for blowfish, rijndael, etc.

rdar://12870177

llvm-svn: 170581

llvm-svn: 170578

When the least bit of C is greater than V, (x&C) must be greater than V
if it is not zero, so the comparison can be simplified.

Although this was suggested in Target/X86/README.txt, it benefits any
architecture with a directly testable form of AND.

Patch by Kevin Schoedel

llvm-svn: 170576

There's probably a better expansion for those nodes than the default for
altivec, but this is better than crashing. VSELECTs occur in loop vectorizer
output.

llvm-svn: 170551

Accordingly, add MVT::getVT.

llvm-svn: 170550

llvm-svn: 170547

I cannot reproduce it the failures locally, so I will keep an eye at the ppc
bots. This patch does add the change to the "Disassembly of section" message,
but that is not what was failing on the bots.

Original message:

Add a funciton to get the segment name of a section.

On MachO, sections also have segment names. When a tool looking at a .o file
prints a segment name, this is what they mean. In reality, a .o has only one
anonymous, segment.

This patch adds a MachO only function to fetch that segment name. I named it
getSectionFinalSegmentName since the main use for the name seems to be infor
the linker with segment this section should go to.

The patch also changes MachOObjectFile::getSectionName to return just the
section name instead of computing SegmentName,SectionName.

llvm-svn: 170545

llvm-svn: 170544

llvm-svn: 170540

instead of EVTs.

llvm-svn: 170538

MVTs, instead of EVTs.

llvm-svn: 170537

from EVT.

llvm-svn: 170536

EVTs.

llvm-svn: 170535

EVTs.

llvm-svn: 170534

of EVT.

llvm-svn: 170532

This changes adds shadow and origin propagation for unknown intrinsics
by examining the arguments and ModRef behaviour. For now, only 3 classes
of intrinsics are handled:
- those that look like simple SIMD store
- those that look like simple SIMD load
- those that don't have memory effects and look like arithmetic/logic/whatever
  operation on simple types.

llvm-svn: 170530

instead of EVTs.

llvm-svn: 170529

MapVector is a bit heavyweight, but I don't see a simpler way. Also the
InductionList is unlikely to be large. This should help 3-stage selfhost
compares (PR14647).

llvm-svn: 170528

llvm-svn: 170524

llvm-svn: 170523

EVT.

llvm-svn: 170522

llvm-svn: 170518

llvm-svn: 170517

Inline the 'hasIncompatibleWithVarArgsAttrs' method into its only uses. And some minor comment reformatting.

llvm-svn: 170516

llvm-svn: 170510

llvm-svn: 170506

bitwidth op back to the original size. If we reduce ANDs then this can cause
an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits
are equal or smaller than the size of the reduced operation.

llvm-svn: 170505

Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.

llvm-svn: 170502

llvm-svn: 170497

llvm-svn: 170496

Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition.

llvm-svn: 170495

llvm-svn: 170493

llvm-svn: 170486

instructions in the assembly code variant if one exists.

The intended use for this is so tools like lldb and darwin's otool(1)
can be switched to print Intel-flavored disassembly.

I discussed extensively this API with Jim Grosbach and we feel
while it may not be fully general, in reality there is only one syntax
for each assembly with the exception of X86 which has exactly
two for historical reasons.

rdar://10989182

llvm-svn: 170477

The bundle_iterator::operator++ function now doesn't need to dig out the
basic block and check against end(). It can use the isBundledWithSucc()
flag to find the last bundled instruction safely.

Similarly, MachineInstr::isBundled() no longer needs to look at
iterators etc. It only has to look at flags.

llvm-svn: 170473

 InstCombine for unsafe floating-point add/sub.

llvm-svn: 170471

Enable the loop vectorizer in clang and not in the pass manager, so that we can disable it in clang.

llvm-svn: 170470