llvm-svn: 84652

encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.

llvm-svn: 84640

llvm-svn: 84632

llvm-svn: 84628

llvm-svn: 84614

present.

llvm-svn: 84613

llvm-svn: 84611

llvm-svn: 84600

functions are not needed.

llvm-svn: 84587

llvm-svn: 84585

llvm-svn: 84583

reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.

llvm-svn: 84582

llvm-svn: 84579

llvm-svn: 84577

llvm-svn: 84575

llvm-svn: 84573

Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572

Patch by Johnny Chen.

llvm-svn: 84570

no functionality change.

llvm-svn: 84567

by ignoring all implicit regs when lowering.

llvm-svn: 84566

llvm-svn: 84565

llvm-svn: 84563

llvm-svn: 84562

llvm-svn: 84561

like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)

llvm-svn: 84558

appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.

llvm-svn: 84554

llvm-svn: 84553

_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.

llvm-svn: 84546

broken makefile deps :(

llvm-svn: 84544

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 

llvm-svn: 84543

lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)

llvm-svn: 84542

llvm-svn: 84540

llvm-svn: 84536

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 

llvm-svn: 84535

we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 

llvm-svn: 84532

llvm-svn: 84531

through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".

llvm-svn: 84530

"something" when printing MCInsts, it will just be missing all the 
operand info.

llvm-svn: 84528

llvm-svn: 84527

All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526