responsible for figuring out what that's supposed to be on its own.

llvm-svn: 101844

where multiple blocks are emitted; functions which do this need to return
the new BB so that their callers can stay current.

llvm-svn: 101843

the intrinsics.  The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type.  The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.

llvm-svn: 101840

llvm-svn: 101839

llvm-svn: 101832

and End arguments by-value rather than by-reference.

llvm-svn: 101830

llvm-svn: 101827

an argument to things that need it.

llvm-svn: 101825

llvm-svn: 101824

need it, just pass around the parent block of the current instruction
explicitly.

llvm-svn: 101822

just ask ScalarEvolution for it on demand. This helps IVUsers be more robust
in the case of expressions changing underneath it. This fixes PR6862.

llvm-svn: 101819

Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.

llvm-svn: 101817

llvm-svn: 101812

llvm-svn: 101808

fetch one from the MachineFunction.

llvm-svn: 101807

llvm-svn: 101806

llvm-svn: 101805

than just getting one through a TargetLowering.

llvm-svn: 101802

SelectionDAG-specific.

llvm-svn: 101801

be done with const_cast.

llvm-svn: 101798

llvm-svn: 101793

llvm-svn: 101790

llvm-svn: 101789

instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)
llvm-svn: 101788

llvm-svn: 101785

VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.

llvm-svn: 101784

llvm-svn: 101783

llvm-svn: 101782

llvm-svn: 101781

llvm-svn: 101779

llvm-svn: 101778

llvm-svn: 101777

llvm-svn: 101776

llvm-svn: 101755

FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754

llvm-svn: 101723

llvm-svn: 101711

llvm-svn: 101710

platforms to unbreak the darwin and linux builds. The BSD folks should feel
free to change the #if, if this breaks them.

llvm-svn: 101703

llvm-svn: 101702