This function verifies the consistency of cached data in the
MachineTraceMetrics analysis.

llvm-svn: 160976

The MachineTraceMetrics analysis must be invalidated before modifying
the CFG. This will catch some of the violations of that rule.

llvm-svn: 160969

A->isPredecessor(B) is the same as B->isSuccessor(A), but it can
tolerate a B that is null or dangling. This shouldn't happen normally,
but it it useful for verification code.

llvm-svn: 160968

Together with Ran Chachick <ran.chachick@intel.com>

llvm-svn: 160954

llvm-svn: 160953

Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.

llvm-svn: 160951

llvm-svn: 160942

llvm-svn: 160941

Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.

llvm-svn: 160939

llvm-svn: 160938

llvm-svn: 160937

llvm-svn: 160927

llvm-svn: 160922

llvm-svn: 160921

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276

llvm-svn: 160919

llvm-svn: 160914

llvm-svn: 160913

It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.

llvm-svn: 160912

Jakob fixed ProcessImplicifDefs in r159149.

llvm-svn: 160910

llvm-svn: 160905

This makes it possible to quickly detect blocks that are outside the
trace.

llvm-svn: 160904

all tests accordingly.

Fixes PR13351.

Patch by shinichiro hamaji!

llvm-svn: 160899

llvm-svn: 160898

llvm-svn: 160897

into predecessor blocks to enable tail call optimization.

rdar://11958338

llvm-svn: 160894

A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.

llvm-svn: 160893

This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.

llvm-svn: 160892

llvm-svn: 160889

Patch by Tyler Nowicki!

llvm-svn: 160888

llvm-svn: 160880

llvm-svn: 160876

This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW

llvm-svn: 160874

llvm-svn: 160873

Move some functions from MCRegisterInfo.h that don't need to be inline.

This shrinks llc by 8K.

llvm-svn: 160865

replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.

llvm-svn: 160841

llvm-svn: 160835

llvm-svn: 160833

I'll remove these two sub-register indexes shortly.

llvm-svn: 160831

The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but
copyPhysReg does the right thing with it. (The old pattern would
eventually produce the same cross-class copy).

llvm-svn: 160830

llvm-svn: 160823