integrated-as.

llvm-svn: 128431

Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417

llvm-svn: 128405

llvm-svn: 128338

llvm-svn: 128322

masks to match inversely for the code as is to work. For the example given
we actually want:

bfi r0, r2, #1, #1

not #0, however, given the way the pattern is written it's not possible
at the moment.

Fixes rdar://9177502

llvm-svn: 128320

Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304

DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass.  Add two test cases.

rdar://problem/9182892

llvm-svn: 128299

t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293

llvm-svn: 128286

Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm.  Modify the disassembler to handle that.

rdar://problem/9184053

llvm-svn: 128285

rdar://problem/9186136

llvm-svn: 128283

Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

llvm-svn: 128254

Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252

llvm-svn: 128244

llvm-svn: 128243

llvm-svn: 128241

These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240

llvm-svn: 128238

llvm-svn: 128236

Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234

The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.

llvm-svn: 128227

VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

llvm-svn: 128226

a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.

llvm-svn: 128220

FIXME: Some cleanups would be needed.
llvm-svn: 128206

entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354

llvm-svn: 128203

CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.

Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^

llvm-svn: 128192

These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.

llvm-svn: 128191

We now tag them as IndexModePost.

llvm-svn: 128189

were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.

llvm-svn: 128186

llvm-svn: 128183

I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.

llvm-svn: 128181

int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742

llvm-svn: 128179

(target-specific branchless method for double-width relational comparisons on x86)

llvm-svn: 128175

This fixes 464.h264ref with the integrated assembler.

llvm-svn: 128172

- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64

llvm-svn: 128153

Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.

llvm-svn: 128122

We now tag them as IndexModePost.

This fixed http://llvm.org/bugs/show_bug.cgi?id=9530.

llvm-svn: 128113

llvm-svn: 128107

VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions.  Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.

Also add a test case.

llvm-svn: 128103