When a PHI use is <undef>, don't emit a copy in the predecessor block,
but insert an IMPLICIT_DEF instruction instead. This ensures that
virtual register uses are always jointly dominated by defs, even if some
of them are IMPLICIT_DEF.

llvm-svn: 159121

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

llvm-svn: 148594

1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

This flag is true from isel to register allocation when the machine
function is required to be in SSA form.  The TwoAddressInstructionPass
and PHIElimination passes clear the flag.

The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.

llvm-svn: 136532

llvm-svn: 130068

llvm-svn: 127398

llvm-svn: 125727

llvm-svn: 125726

llvm-svn: 125476

This time let's rephrase to trick gcc-4.3 into not miscompiling.

llvm-svn: 123432

llvm-svn: 123423

Fix some callers to better deal with debug values.

llvm-svn: 123419

llvm-svn: 123389

It will still return an iterator that points to the first terminator or end(),
but there may be DBG_VALUE instructions following the first terminator.

llvm-svn: 123384

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107

llvm-svn: 120959

function so that it can be shared with StrongPHIElimination.

llvm-svn: 120951

llvm-svn: 120918

llvm-svn: 115996

Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API.

llvm-svn: 111815

llvm-svn: 111366

PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed.

llvm-svn: 111285

Move the decision logic whether it's a good idea to split a critical edge to clients. Also fixed an erroneous check. An edge is only a back edge when the from and to blocks are in the same loop.

llvm-svn: 111256

PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994

good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2

llvm-svn: 111221

llvm-svn: 110460

llvm-svn: 110410

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.

This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.

llvm-svn: 108050

into a utility routine, teach it how to update MachineLoopInfo, and
make use of it in MachineLICM to split critical edges on demand.

llvm-svn: 106555

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103109

Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...

PHI elimination now does more than phi elimination. It is really a de-SSA pass.

llvm-svn: 103039

llvm-svn: 103013

llvm-svn: 99465

llvm-svn: 97687

Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply
defined registers. That doesn't work if the phi join is implicitly defined in
all but one of the predecessors.

llvm-svn: 96994

llvm-svn: 96837

llvm-svn: 96496