something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310

they are just as useless, but at least a bit more gramatical

llvm-svn: 122305

llvm-svn: 122259

ARM (and other 32-bit-only) targets support for i8 and i16 overflow 
multiplies.  The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.

llvm-svn: 122221

Imagine we see:

EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS

Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor.  However, it also uses the EFLAGS
of the predecessor, so it is safe to emit.  SDep edges ensure that
the right order happens already anyway.

This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.

llvm-svn: 122211

llvm-svn: 122209

llvm-svn: 122208

llvm-svn: 122193

enough to teach it that ADDE(0,0) is known 0 except the 
low bit, for example.

llvm-svn: 122191

isel is *required* to split the edge.  PHI values get evaluated
on the edge, not in their predecessor block.

llvm-svn: 122170

BUILD_VECTOR operands where the element type is not legal.  I had previously
changed this code to insert TRUNCATE operations, but that was just wrong.

llvm-svn: 122102

code for the case where 32-bit divide by constant is
turned into 64-bit multiply by constant.  8771012.

llvm-svn: 122090

Radar 8776599

llvm-svn: 122018

a wider mul if the wider mul is legal.

llvm-svn: 121848

result, the top bits are truncated off anyway, just use SRL.

llvm-svn: 121846

when the wider type is legal.  This allows us to compile:

define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
	%div = udiv i16 %x, 33
	ret i16 %div
}

into:

test1:                                  # @test1
	movzwl	4(%esp), %eax
	imull	$63551, %eax, %eax      # imm = 0xF83F
	shrl	$21, %eax
	ret

instead of:

test1:                                  # @test1
        movw    $-1985, %ax             # imm = 0xFFFFFFFFFFFFF83F
        mulw    4(%esp)
        andl    $65504, %edx            # imm = 0xFFE0
        movl    %edx, %eax
        shrl    $5, %eax
        ret

Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320

We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.

llvm-svn: 121696

llvm-svn: 121662

catch this here rather than later after accessing uninitialized memory
etc.  Fires when compiling the testcase in PR8237.

llvm-svn: 121635

Necessary for byval support on ARM.  Radar 7662569.

llvm-svn: 121412

llvm-svn: 121356

llvm-svn: 121293

zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

llvm-svn: 121120

If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.

llvm-svn: 121059

llvm-svn: 120910

setAllBits(), setBit(unsigned), etc.

llvm-svn: 120564

legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501

and use this to disable a specific optimization.  Patch by Micah Villmow!

llvm-svn: 120435

llvm-svn: 120413

llvm-svn: 120298

llvm-svn: 120235

llvm-svn: 119990

This currently only catches the most basic case, a two-case switch, but can be
extended later.

llvm-svn: 119964

llvm-svn: 119903

so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901

Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.

llvm-svn: 119898

llvm-svn: 119875

DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.

llvm-svn: 119819

not anyext(select).  Spotted by Frits van Bommel.

llvm-svn: 119739

if the extension types were not the same.  The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext).  Reported
and diagnosed by Sebastien Deldon.

llvm-svn: 119728

memset; we may need it to decide between MOVAPS and MOVUPS
later.  Adjust a test that was looking for wrong code.
PR 3866 / 8675131.

llvm-svn: 119605