By the way, this code is buggy. You can't keep a map<MDNode *, something>
because the MDNode may be destroyed and reused for something else.

llvm-svn: 83141

per customary usage

llvm-svn: 83137

the size of the saved frame pointer needs to be taken into account.

llvm-svn: 83136

Patch by Sylvere Teissier.

llvm-svn: 83135

llvm-svn: 83132

section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.

llvm-svn: 83127

llvm-svn: 83123

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

llvm-svn: 83122

information.  This allows arbitrary code involving DW_OP_plus_uconst
and DW_OP_deref.  The scheme allows for easy extention to include,
any, or all of the DW_OP_ opcodes.  I thought about just exposing all
of them, but, wasn't sure if people wanted the dwarf opcodes exposed
in the api.  Is that a layering violation?

With this scheme, the entire existing block scheme used by llvm-gcc
can be switched over to the new scheme.  I think that would be
cleaner, as then the compiler specific bits are not present in llvm
proper.  Before the old code can be yanked however, similar code in
clang would have to be removed.

Next up, more testing.

llvm-svn: 83120

llvm-svn: 83117

Lookup handler name only when assertions are enabled.

llvm-svn: 83114

llvm-svn: 83107

llvm-svn: 83105

llvm-svn: 83103

llvm-svn: 83102

Remove unnecessary cast.

llvm-svn: 83100

llvm-svn: 83083

so a simple "current register" will suffice. Also add some additional
sanity-checking assertions to make sure things are as we expect.

llvm-svn: 83081

the instruction we're scavenging for. The scavenger needs to know to avoid
them when analyzing register usage.

llvm-svn: 83077

llvm-svn: 83058

llvm-svn: 83033

slot for the register scavenger when compiling Thumb1 functions.

llvm-svn: 83023

llvm-svn: 83021

llvm-svn: 83019

llvm-svn: 83016

the operands, rather than trying to partition them into a start
and a step. This handles non-affine add recurrences correctly.

llvm-svn: 83011

llvm-svn: 83010

llvm-svn: 83008

llvm-svn: 83007

unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006

llvm-svn: 83001

llvm-svn: 82999

llvm-svn: 82995

llvm-svn: 82994

llvm-svn: 82993

llvm-svn: 82991

llvm-svn: 82990

Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

Disable rematting of it for now.

llvm-svn: 82975