llvm-svn: 79107

llvm-svn: 79101

llvm-svn: 79098

PIC16DebugInfo currently rely on NameStr of composite type descriptors to uniquely
identify debug info for two aggregate type decls with same name.
This implementation will change when we have MDNodes based debug info implemenatation in place

llvm-svn: 79097

llvm-svn: 79094

The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.

llvm-svn: 79091

llvm-svn: 79084

llvm-svn: 79082

the class it defines.

llvm-svn: 79081

llvm-svn: 79080

support for globals going into the appropriate sections with the flags.

This hopefully finishes unbreaking the previous behavior that I broke before.

llvm-svn: 79079

them to null out the default section pointers.

llvm-svn: 79078

class which represents the XCore cp/dp section flags.  No functionality
change yet.

llvm-svn: 79077

"the current basic block".

llvm-svn: 79069

llvm-svn: 79067

the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.

llvm-svn: 79061

llvm-svn: 79039

libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033

llvm-svn: 79032

llvm-svn: 79030

llvm-svn: 79026

llvm-svn: 79024

llvm-svn: 79022

llvm-svn: 79015

llvm-svn: 79014

llvm-svn: 79012

llvm-svn: 79009

as well as the StringRef change.

llvm-svn: 79006

implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.

llvm-svn: 78995

scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994

target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993

specific printer (this only works on x86, for now).
 - This makes it possible to do some correctness checking of the parsing and
   matching, since we can compare the results of 'as' on the original input, to
   those of 'as' on the output from llvm-mc.

 - In theory, we could now have an easy ATT -> Intel syntax converter. :)

llvm-svn: 78986

to print one instruction.

llvm-svn: 78985

llvm-svn: 78984

llvm-svn: 78970

llvm-svn: 78968

accidentally match unrelated things.

llvm-svn: 78966

AsmPrinter instance (instead of just a FunctionPass)

llvm-svn: 78962

must be emitted for PowerPC-Linux '.bss' section

llvm-svn: 78958

llvm-svn: 78948