llvm-svn: 100691

ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690

llvm-svn: 100645

a co-committed clang patch.

llvm-svn: 100485

When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384

member of AsmPrinter.  Instead, pass it in explicitly.

llvm-svn: 100306

llvm-svn: 100268

llvm-svn: 100267

is expected.

llvm-svn: 100247

llvm-svn: 100244

(Fix build failure)

llvm-svn: 100243

backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233

llvm-svn: 100034

PR6753.

llvm-svn: 100032

doesn't need to be stable because the patterns are fully ordered.

Add a first level sort predicate that orders patterns in this
order:  1) scalar integer operations 2) scalar floating point 
3) vector int 4) vector float.  This is a trivial sort on their
top level pattern type so it is nice and transitive.  The
benefit of doing this is that simple integer operations are
much more common than insane vector things and isel was trying
to match the big complex vector patterns before the simple
ones because the complexity of the vector operations was much
higher.  Since they can't both match, it is best (for compile
time) to try the simple integer ones first.

This cuts down the # failed match attempts on real code by
quite a bit, for example, this reduces backtracks on crafty
(as a random example) from 228285 -> 188369.

llvm-svn: 99797

llvm-svn: 99796

patterns within the generated matcher.  This works great except
that the sort fails because the relation defined isn't 
transitive.  I have a much simpler solution coming next, but want
to archive the code.

llvm-svn: 99795

comment in the generated table.

llvm-svn: 99794

where an incorrect number of operands is provided to an sdnode instead
of just a few cases.

llvm-svn: 99761

and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)

llvm-svn: 99759

transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.

llvm-svn: 99756

llvm-svn: 99747

by rotating it.

llvm-svn: 99746

llvm-svn: 99744

1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.

llvm-svn: 99740

issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.

llvm-svn: 99728

same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.

llvm-svn: 99727

from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.

llvm-svn: 99726

results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.

llvm-svn: 99725

the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.

llvm-svn: 99722

llvm-svn: 99714

llvm-svn: 99703

Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539

use with Python's unittest.

llvm-svn: 99498

bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648

llvm-svn: 99494

If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

llvm-svn: 99492

in some more places.

llvm-svn: 99366

instead of reimplementing it wrong and poorly.

llvm-svn: 99357

llvm-svn: 99354

llvm-svn: 99353