llvm-svn: 78544

llvm-svn: 78543

llvm-svn: 78540

llvm-svn: 78534

llvm-svn: 78533

make it easier to see interesting ambiguities.
 - Also, check that user doesn't try to redefine the super class. This is a wart
   in the current design, in that assembler match classes aren't explicitly
   declared somewhere (so there isn't a unique place to declare the super
   class). This should probably be fixed.

llvm-svn: 78532

llvm-svn: 78531

 - We can now discriminate SUB32ri8 from SUB32ri, for example.

llvm-svn: 78530

llvm-svn: 78529

llvm-svn: 78528

 - We want the ordering operation to be simple, since we run it on every
   match. The old ordering is also not a strict weak ordering when there are
   ambiguities, which makes MSVC unhappy.

 - While we are at it, detect all ambiguities instead of just the adjacent
   ones. There are actually 655, for X86.

llvm-svn: 78526

take the table vectors as separate arguments, instead of the previous
approach where they were combined into one big vector.

llvm-svn: 78525

classes for X86.

llvm-svn: 78524

 -2 FIXMEs.

llvm-svn: 78523

ambiguities.
 - Currently there are 483 ambiguities to resolve. :)

llvm-svn: 78522

llvm-svn: 78521

llvm-svn: 78520

llvm-svn: 78518

This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)

llvm-svn: 78517

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514

 - Track whether we need to insert an explicit 'break'.

 - Invert conditional when matching a single prefix to reduce
   nesting/bracing/breaking.

 - wc -l of X86GenAsmMatcher.inc decreased by 10%. :)

llvm-svn: 78513

llvm-svn: 78512

llvm-svn: 78511

2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and 
   TLOFELF::AtIsCommentChar.

llvm-svn: 78510

llvm-mc's purpose yet and we'll want to switch to creating semantic sections
at some point.

llvm-svn: 78509

bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508

llvm-svn: 78506

llvm-svn: 78505

Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.

llvm-svn: 78504

 --- Reverse-merging r78501 into '.':
U    lib/Target/PIC16/PIC16TargetObjectFile.cpp
D    lib/Target/PIC16/PIC16Section.h

llvm-svn: 78503

llvm-svn: 78501

MCSection instances.

llvm-svn: 78500

llvm-svn: 78499

A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.

llvm-svn: 78498

Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.

llvm-svn: 78497

llvm-svn: 78496

give the impls an object-file-specific name.  In the future
they can take different arguments etc.

llvm-svn: 78495

now that they create *all* the sections.

llvm-svn: 78494

llvm-svn: 78493

much more efficient way than a sequence of if's.  Switch MatchRegisterName
to use it.  It would be nice if someone could factor this out to a shared
place in tblgen :)

llvm-svn: 78492