- Jan 03, 2012
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Jakob Stoklund Olesen authored
This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
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Nadav Rotem authored
llvm-svn: 147485
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Nadav Rotem authored
llvm-svn: 147484
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Chad Rosier authored
then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 llvm-svn: 147481
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Nick Lewycky authored
if-statement by turning it into an assert. No functionality change. llvm-svn: 147474
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Owen Anderson authored
Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
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Lang Hames authored
llvm-svn: 147471
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Stepan Dyatkovskiy authored
llvm-svn: 147470
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Matt Beaumont-Gay authored
If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
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Eric Christopher authored
llvm-svn: 147456
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Nick Lewycky authored
llvm-svn: 147454
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Devang Patel authored
llvm-svn: 147453
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Stepan Dyatkovskiy authored
llvm-svn: 147446
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Elena Demikhovsky authored
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
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- Jan 02, 2012
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Andrew Trick authored
"phony" insertion point. Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert llvm-svn: 147439
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Duncan Sands authored
llvm-svn: 147435
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Chandler Carruth authored
is testing the bitcode reader's functionality, not VMCore's. Add the what is a hope sufficient build system mojo to build and run a new unittest. Also clean up some of the test's naming. The goal for the file should be to unittest the Bitcode Reader, and this is just one particular test among potentially many in the future. Also, reverse my position and relegate the PR# to a comment, but stash the comment on the same line as the test name so it doesn't get lost. This makes the code more self-documenting hopefully w/o losing track of the PR number. llvm-svn: 147431
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Craig Topper authored
Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions. llvm-svn: 147430
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Craig Topper authored
Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection. llvm-svn: 147428
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Chandler Carruth authored
build. This didn't show up in the CMake build because the CMake build for the unittests is rather poorly factored. This probably isn't the correct fix. This should be a bitcode reader unittest not a VMCore unittest. I'll move it and clean various parts of the unittest up in a follow-up patch, but I wanted to unbreak the bots. llvm-svn: 147427
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Nadav Rotem authored
Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit. llvm-svn: 147426
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Rafael Espindola authored
PR11677. llvm-svn: 147425
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- Jan 01, 2012
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Craig Topper authored
llvm-svn: 147411
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Craig Topper authored
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. llvm-svn: 147409
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Benjamin Kramer authored
llvm-svn: 147404
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Benjamin Kramer authored
PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers. llvm-svn: 147403
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Benjamin Kramer authored
llvm-svn: 147402
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Rafael Espindola authored
llvm-svn: 147400
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Elena Demikhovsky authored
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
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NAKAMURA Takumi authored
llvm-svn: 147395
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Craig Topper authored
llvm-svn: 147394
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Craig Topper authored
llvm-svn: 147393
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Craig Topper authored
Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected. llvm-svn: 147392
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- Dec 31, 2011
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Nick Lewycky authored
'and' that would zero out the trailing bits, and to produce an exact shift ourselves. llvm-svn: 147391
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Dylan Noblesmith authored
See PR11652. Trying to add this assert to setSubclassData() itself actually prevented the miscompile entirely, so it has to be here. This makes the source of the bug more obvious than the other asserts triggering later on did. llvm-svn: 147390
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- Dec 30, 2011
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Bruno Cardoso Lopes authored
llvm-svn: 147383
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Bruno Cardoso Lopes authored
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue for jmptarget and brtarget Mips tablegen operand types in the code emitter for old-style JIT. Rename the pc relative relocation for branches - new name is Mips::reloc_mips_pc16. Patch by Sasa Stankovic llvm-svn: 147382
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Nick Lewycky authored
llvm-svn: 147379
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Craig Topper authored
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. llvm-svn: 147369
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Craig Topper authored
llvm-svn: 147368
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