- Jan 03, 2012
-
-
Jakob Stoklund Olesen authored
This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
-
Nadav Rotem authored
llvm-svn: 147484
-
Owen Anderson authored
Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
-
Lang Hames authored
llvm-svn: 147471
-
Nick Lewycky authored
llvm-svn: 147454
-
Elena Demikhovsky authored
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
-
- Jan 01, 2012
-
-
Rafael Espindola authored
llvm-svn: 147400
-
Elena Demikhovsky authored
The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147399
-
- Dec 28, 2011
-
-
Nadav Rotem authored
Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
-
- Dec 26, 2011
-
-
Eli Friedman authored
Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. llvm-svn: 147283
-
- Dec 25, 2011
-
-
Nadav Rotem authored
llvm-svn: 147272
-
- Dec 23, 2011
-
-
Dylan Noblesmith authored
llvm-svn: 147197
-
- Dec 22, 2011
-
-
Pete Cooper authored
llvm-svn: 147127
-
Pete Cooper authored
Fixes <rdar://problem/10584116> llvm-svn: 147125
-
Jakub Staszak authored
don't get any serious benefit there. llvm-svn: 147101
-
- Dec 21, 2011
-
-
Jakub Staszak authored
- Add some constantness. llvm-svn: 147090
-
Lang Hames authored
Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file. llvm-svn: 147089
-
Lang Hames authored
llvm-svn: 147088
-
Jakob Stoklund Olesen authored
llvm-svn: 147071
-
- Dec 20, 2011
-
-
Lang Hames authored
llvm-svn: 146987
-
Jakub Staszak authored
llvm-svn: 146986
-
Chandler Carruth authored
likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
-
-
Dan Gohman authored
llvm-svn: 146927
-
- Dec 19, 2011
-
-
Evan Cheng authored
unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 llvm-svn: 146914
-
Eli Friedman authored
llvm-svn: 146897
-
Jakob Stoklund Olesen authored
Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. llvm-svn: 146874
-
- Dec 18, 2011
-
-
Joerg Sonnenberger authored
attribute themselve. llvm-svn: 146851
-
- Dec 17, 2011
-
-
Rafael Espindola authored
asm parsing and testcase. llvm-svn: 146801
-
Eric Christopher authored
llvm-svn: 146784
-
Eric Christopher authored
llvm-svn: 146783
-
Eric Christopher authored
llvm-svn: 146780
-
- Dec 15, 2011
-
-
Nick Lewycky authored
llvm-svn: 146702
-
Devang Patel authored
Patch by Kyriakos Georgiou! llvm-svn: 146670
-
Eli Friedman authored
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. llvm-svn: 146630
-
Owen Anderson authored
Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default. llvm-svn: 146623
-
Dan Gohman authored
into Analysis as a standalone function, since there's no need for it to be in VMCore. Also, update it to use isKnownNonZero and other goodies available in Analysis, making it more precise, enabling more aggressive optimization. llvm-svn: 146610
-
Devang Patel authored
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
-
- Dec 14, 2011
-
-
Bill Wendling authored
with the correct iterator. <rdar://problem/10530851> llvm-svn: 146600
-
Evan Cheng authored
r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
-