This can only happen if the set of reserved registers changes during
register allocation.

<rdar://problem/10625436>

llvm-svn: 147486

llvm-svn: 147484

Remove the restriction that target intrinsics can only involve legal types.  Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization.  For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's.  ARM already does some expansions like this for non-intrinsic operations.

llvm-svn: 147472

llvm-svn: 147471

llvm-svn: 147454

The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147445

llvm-svn: 147400

The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147399

Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage.

llvm-svn: 147309

Make sure DAGCombiner doesn't introduce multiple loads from the same memory location.  PR10747, part 2.

llvm-svn: 147283

llvm-svn: 147272

llvm-svn: 147197

llvm-svn: 147127

Fixes <rdar://problem/10584116>

llvm-svn: 147125

don't get any serious benefit there.

llvm-svn: 147101

- Add some constantness.

llvm-svn: 147090

Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file.

llvm-svn: 147089

llvm-svn: 147088

llvm-svn: 147071

llvm-svn: 146987

llvm-svn: 146986

likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966

llvm-svn: 146960

llvm-svn: 146927

unpredicated. That is, turn
 subeq  r0, r1, #1
 addne  r0, r1, #1                                                                                                                                                                                                     
into
 sub    r0, r1, #1
 addne  r0, r1, #1

For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
 op    r1, ...
 str   r1, [r10]        ; end-of-life of r1 as div result
 cmp   r0, #65
 movne r1, #44  ; raw dependency on previous r1
 moveq r1, #12

If movne is unpredicated, then
 op    r1, ...
 str   r1, [r10]
 cmp   r0, #65
 mov   r1, #44  ; r1 written unconditionally
 moveq r1, #12

Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.

This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.

rdar://8951196

llvm-svn: 146914

llvm-svn: 146897

Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.

This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.

llvm-svn: 146874

attribute themselve.

llvm-svn: 146851

asm parsing and testcase.

llvm-svn: 146801

llvm-svn: 146784

llvm-svn: 146783

llvm-svn: 146780

llvm-svn: 146702

Patch by Kyriakos Georgiou!

llvm-svn: 146670

Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.

llvm-svn: 146630

Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls.  These are already marked as illegal by default.

llvm-svn: 146623

into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610

On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604

with the correct iterator.
<rdar://problem/10530851>

llvm-svn: 146600

r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.

llvm-svn: 146583