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  1. Jan 03, 2012
  2. Jan 01, 2012
    • Rafael Espindola's avatar
      Revert 147399. It broke CodeGen/ARM/vext.ll. · d3df9401
      Rafael Espindola authored
      llvm-svn: 147400
      d3df9401
    • Elena Demikhovsky's avatar
      Fixed a bug in SelectionDAG.cpp. · 67f80c34
      Elena Demikhovsky authored
      The failure seen on win32, when i64 type is illegal.
      It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.
      
      The failure message is:
      llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.
      
      I added a special test that checks vector shuffle on win32.
      
      llvm-svn: 147399
      67f80c34
  3. Dec 28, 2011
    • Nadav Rotem's avatar
      PR11662. · 3c3dd6e5
      Nadav Rotem authored
      Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage.
      
      llvm-svn: 147309
      3c3dd6e5
  4. Dec 26, 2011
  5. Dec 25, 2011
  6. Dec 23, 2011
  7. Dec 22, 2011
  8. Dec 21, 2011
  9. Dec 20, 2011
  10. Dec 19, 2011
    • Evan Cheng's avatar
      Add a if-conversion optimization that allows 'true' side of a diamond to be · 4266a793
      Evan Cheng authored
      unpredicated. That is, turn
       subeq  r0, r1, #1
       addne  r0, r1, #1                                                                                                                                                                                                     
      into
       sub    r0, r1, #1
       addne  r0, r1, #1
      
      For targets where conditional instructions are always executed, this may be
      beneficial. It may remove pseudo anti-dependency in out-of-order execution
      CPUs. e.g.
       op    r1, ...
       str   r1, [r10]        ; end-of-life of r1 as div result
       cmp   r0, #65
       movne r1, #44  ; raw dependency on previous r1
       moveq r1, #12
      
      If movne is unpredicated, then
       op    r1, ...
       str   r1, [r10]
       cmp   r0, #65
       mov   r1, #44  ; r1 written unconditionally
       moveq r1, #12
      
      Both mov and moveq are no longer depdendent on the first instruction. This gives
      the out-of-order execution engine more freedom to reorder them.
      
      This has passed entire LLVM test suite. But it has not been enabled for any ARM
      variant pending more performance evaluation.
      
      rdar://8951196
      
      llvm-svn: 146914
      4266a793
    • Eli Friedman's avatar
      5bb6826f
    • Jakob Stoklund Olesen's avatar
      Handle sub-register operands in recomputeRegClass(). · 8f9c6c4a
      Jakob Stoklund Olesen authored
      Now that getMatchingSuperRegClass() returns accurate results, it can be
      used to compute constraints imposed by instructions using a sub-register
      of a virtual register.
      
      This means we can recompute the register class of any virtual register
      by combining the constraints from all its uses.
      
      llvm-svn: 146874
      8f9c6c4a
  11. Dec 18, 2011
  12. Dec 17, 2011
  13. Dec 15, 2011
  14. Dec 14, 2011
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