Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363

llvm-svn: 140291

llvm-svn: 140214

yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046

with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159

llvm-svn: 138751

needed for Mips32.

llvm-svn: 138132

piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007

anonymous namespace.

llvm-svn: 137975

llvm-svn: 137892

llvm-svn: 137848

llvm-svn: 137831

llvm-svn: 137804

llvm-svn: 137515

New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.

I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813

llvm-svn: 136283

llvm-svn: 135537

llvm-svn: 135522

ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520

llvm-svn: 135514

llvm-svn: 135496

- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495

basic blocks.

llvm-svn: 135490

ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465

llvm-svn: 135464

llvm-svn: 135418

moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415

virtual registers are used. 

llvm-svn: 135403

llvm-svn: 135375

is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742

llvm-svn: 134661

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 134087

Part of rdar://9643582

llvm-svn: 134084

 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811

llvm-svn: 133496

llvm-svn: 133494

llvm-svn: 133118

llvm-svn: 132777

No functional change.

Part of PR6965

llvm-svn: 132763