saving and restoring them.

llvm-svn: 131745

llvm-svn: 131739

llvm-svn: 131730

llvm-svn: 131724

Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic

llvm-svn: 131714

llvm-svn: 131711

This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 

llvm-svn: 131710

llvm-svn: 131709

llvm-svn: 131708

llvm-svn: 131689

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674

Fixes PR9934.

We really need to start tblgening the relocation info :-(

llvm-svn: 131669

llvm-svn: 131668

llvm-svn: 131664

llvm-svn: 131660

llvm-svn: 131657

llvm-svn: 131654

llvm-svn: 131649

llvm-svn: 131642

pseudos.  rdar://problem/8614450

llvm-svn: 131641

verifier failures in the CodeGen/CellSPU tests.

llvm-svn: 131631

llvm-svn: 131630

llvm-svn: 131627

piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.

llvm-svn: 131626

llvm-svn: 131625

add instruction takes an rGPR. This fixes the last of PR8825.

llvm-svn: 131619

llvm-svn: 131597

llvm-svn: 131596

which fixes all of the CodeGen/MBlaze verifier failures.

llvm-svn: 131595

uses them.

llvm-svn: 131591

llvm-svn: 131587

Add test case.

llvm-svn: 131582

llvm-svn: 131578

llvm-svn: 131565

Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.

llvm-svn: 131560

llvm-svn: 131555

Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178

llvm-svn: 131553

Patch by Dan Bailey

llvm-svn: 131537

In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529