RDHWR. 

llvm-svn: 146101

llvm-svn: 146097

llvm-svn: 146096

llvm-svn: 146086

llvm-svn: 146059

PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853

nodes.

llvm-svn: 144841

llvm-svn: 144840

llvm-svn: 144554

llvm-svn: 144448

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 143994

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989

llvm-svn: 143988

llvm-svn: 142216

llvm-svn: 142214

llvm-svn: 142211

source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210

and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207

llvm-svn: 142205

llvm-svn: 141761

instructions with two register operands derive from it.

llvm-svn: 141742

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

the real instructions.

llvm-svn: 141718

llvm-svn: 141715

llvm-svn: 141708

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

Mips64.

llvm-svn: 141618

zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608

for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603

llvm-svn: 141029

llvm-svn: 141028

llvm-svn: 141024

llvm-svn: 141017