llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400

llvm-svn: 139399

llvm-svn: 139389

llvm-svn: 139383

llvm-svn: 139381

Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.

llvm-svn: 139353

removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344

llvm-svn: 139339

llvm-svn: 139329

llvm-svn: 139328

llvm-svn: 139324

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320

single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

llvm-svn: 139311

in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305

Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304

llvm-svn: 139285

More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272

Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270

Remove the "common" set of instructions shared between ARM and Thumb2 modes.  This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.

llvm-svn: 139268

llvm-svn: 139267

llvm-svn: 139264

llvm-svn: 139263

llvm-svn: 139258

llvm-svn: 139256

The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254

llvm-svn: 139251

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

llvm-svn: 139250

Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).

This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245

There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.

llvm-svn: 139243

Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242

llvm-svn: 139240

Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.

llvm-svn: 139237

Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).

llvm-svn: 139234

(not assert) early.

llvm-svn: 139233

llvm-svn: 139232

information for older linkers.

llvm-svn: 139206

llvm-svn: 139202

llvm-svn: 139200