Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021

llvm-svn: 158013

llvm-svn: 158004

llvm-svn: 157981

llvm-svn: 157980

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979

llvm-svn: 157976

llvm-svn: 157972

when a compile time constant is known.  This occurs when implicitly zero 
extending function arguments from 16 bits to 32 bits.

<rdar://problem/11481151>

llvm-svn: 157966

inserted after the shift-left-logical node.

llvm-svn: 157937

llvm-svn: 157935

This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929

llvm-svn: 157920

llvm-svn: 157917

Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 forms of scalar FMA instructions.

llvm-svn: 157914

llvm-svn: 157912

It seems that this no longer causes test suite failures on PPC64 (after r157159),
and often gives a performance benefit, so it can be enabled by default.

llvm-svn: 157911

llvm-svn: 157903

Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit.

llvm-svn: 157898

llvm-svn: 157896

Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior.

llvm-svn: 157895

llvm-svn: 157894

llvm-svn: 157885

llvm-svn: 157872

llvm-svn: 157867

llvm-svn: 157866

llvm-svn: 157865

custom-lower unaligned load and store nodes.

llvm-svn: 157864

llvm-svn: 157863

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862

the MachineOperand type has a valid offset. 

llvm-svn: 157861

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

then DestReg is undefined.

llvm-svn: 157840

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837

This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.

llvm-svn: 157831

Factor out the expansion code into a function.
This change is to be enabled in clang.

rdar://9877866

llvm-svn: 157830

This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

llvm-svn: 157818

llvm-svn: 157805

Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.

llvm-svn: 157804

llvm-svn: 157802