llvm-svn: 148578

llvm-svn: 148570

llvm-svn: 148569

We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568

rdar://10724489

llvm-svn: 148560

For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556

Found by the clang static analyzer.

llvm-svn: 148541

Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.

llvm-svn: 148537

llvm-svn: 148532

llvm-svn: 148513

llvm-svn: 148495

llvm-svn: 148489

llvm-svn: 148486

llvm-svn: 148485

llvm-svn: 148473

llvm-svn: 148467

llvm-svn: 148466

llvm-svn: 148459

llvm-svn: 148456

llvm-svn: 148455

  to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444

llvm-svn: 148442

llvm-svn: 148440

It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438

This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437

Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432

llvm-svn: 148431

llvm-svn: 148427

If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424

llvm-svn: 148422

llvm-svn: 148401

llvm-svn: 148400

Load/store instructions w/ a fixup to be relative a function marked as thumb
don't use the low bit to specify thumb vs. non-thumb like interworking
branches do, so don't set it when dealing with those fixups.

rdar://10348687.

llvm-svn: 148366

llvm-svn: 148364

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363

Move ARM callee-saved lists into ARMCallingConv.td.

llvm-svn: 148357

Add a trivial implementation of the getCallPreservedMask() hook.

llvm-svn: 148347

llvm-svn: 148338

llvm-svn: 148334

llvm-svn: 148322