llvm-svn: 33775

llvm-svn: 33773

llvm-svn: 33772

pessimization where instcombine can sink a load (good for code size) that
prevents an alloca from being promoted by mem2reg (bad for everything).

llvm-svn: 33771

llvm-svn: 33770

llvm-svn: 33769

llvm-svn: 33768

llvm-svn: 33767

llvm-svn: 33766

llvm-svn: 33765

llvm-svn: 33764

llvm-svn: 33763

llvm-svn: 33762

initializing the Res variable to 0 and asserting it is not zero after the
result should have been created.

llvm-svn: 33761

updating.  These were exposed by Devang's recent passmgr changes (with
non-default passorderings) because now the inliner can be interleved with
the LCSSA pass.

llvm-svn: 33760

llvm-svn: 33759

llvm-svn: 33758

llvm-svn: 33757

llvm-svn: 33756

llvm-svn: 33755

llvm-svn: 33754

- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.

llvm-svn: 33753

affected part is codegen of "memove" inside x86 backend. This fixes
PR1144

llvm-svn: 33752

llvm-svn: 33751

llvm-svn: 33750

llvm-svn: 33749

llvm-svn: 33748

llvm-svn: 33747

llvm-svn: 33746

llvm-svn: 33745

to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744

llvm-svn: 33743

llvm-svn: 33742

llvm-svn: 33741

llvm-svn: 33740

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

llvm-svn: 33738

without exiting program.

llvm-svn: 33737

llvm-svn: 33736

llvm-svn: 33735