the handling of eliminating stores to byval arguments.

llvm-svn: 46494

llvm-svn: 46493

sufficiently to have it pass.  I'm removing it from
the testsuite and adding it to PR452 instead.

llvm-svn: 46492

llvm-svn: 46488

generated. This feature would only show up in fairly complex patterns, such
as this one in CellSPU:

  def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
	    (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;

which generated the following emit code:

SDNode *Emit_0(const SDOperand &N, unsigned Opc0, unsigned Opc1, MVT::ValueType VT0, MVT::ValueType VT1) DISABLE_INLINE {
  SDOperand N0 = N.getOperand(0);
  SDOperand N00 = N0.getOperand(0);
  SDOperand N01 = N0.getOperand(1);
  SDOperand N1 = N.getOperand(1);
  SDOperand N10 = N1.getOperand(0);
  SDOperand N11 = N1.getOperand(1);
  SDOperand Tmp3(CurDAG->getTargetNode(Opc0, VT0, N00), 0);
  return CurDAG->SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */
}

Tested against the test suites without incident.

llvm-svn: 46487

llvm-svn: 46486

llvm-svn: 46485

These loops are not yet handled.

Fix PR 1912.

llvm-svn: 46484

only two addressing mode nodes, SPUaform and SPUindirect (vice the
three previous ones, SPUaform, SPUdform and SPUxform). This improves
code somewhat because we now avoid using reg+reg addressing when
it can be avoided. It also simplifies the address selection logic,
which was the main point for doing this.

Also, for various global variables that would be loaded using SPU's
A-form addressing, prefer D-form offs[reg] addressing, keeping the
base in a register if the variable is used more than once.

llvm-svn: 46483

llvm-svn: 46479

unbalanced quotes.

llvm-svn: 46476

Added getValue() to FoldingSetNodeWrapper.

llvm-svn: 46465

llvm-svn: 46458

be marked readonly either.

llvm-svn: 46456

llvm-svn: 46455

llvm-svn: 46454

directories.  Patch by Sam Bishop.

llvm-svn: 46453

llvm-svn: 46451

the function label isn't associated with something it shouldn't be.

llvm-svn: 46449

llvm-svn: 46433

output.  Patch contributed by Sam Bishop!

llvm-svn: 46432

llvm-svn: 46431

llvm-svn: 46429

Patch by Eli Friedman, thanks!

llvm-svn: 46428

way or the other.  Rewriting the code itself prevents subsequent analysis
passes from making contradictory conclusions about the code that could 
cause an infeasible path to be made feasible.

llvm-svn: 46427

llvm-svn: 46425

llvm-svn: 46424

f7/f11 to:

_f7:
	eor r0, r0, #2, 2 @ -2147483648
	bx lr
_f11:
	bic r0, r0, #2, 2 @ -2147483648
	bx lr

instead of:

_f7:
	fmsr s0, r0
	fnegs s0, s0
	fmrs r0, s0
	bx lr

_f11:
	fmsr s0, r0
	fabss s0, s0
	fmrs r0, s0
	bx lr

llvm-svn: 46423

llvm-svn: 46422

llvm-svn: 46421

llvm-svn: 46420

llvm-svn: 46419

llvm-svn: 46417

longer allowed to write through byval arguments.

llvm-svn: 46416

registers if used by a bitconvert or using a bitconvert.  This allows us to
avoid constant pool loads and use cheaper integer instructions when the
values come from or end up in integer regs anyway.  For example, we now 
compile CodeGen/X86/fp-in-intregs.ll to:

_test1:
	movl	$2147483648, %eax
	xorl	4(%esp), %eax
	ret
_test2:
	movl	$1065353216, %eax
	orl	4(%esp), %eax
	andl	$3212836864, %eax
	ret

Instead of:
_test1:
	movss	4(%esp), %xmm0
	xorps	LCPI2_0, %xmm0
	movd	%xmm0, %eax
	ret
_test2:
	movss	4(%esp), %xmm0
	andps	LCPI3_0, %xmm0
	movss	LCPI3_1, %xmm1
	andps	LCPI3_2, %xmm1
	orps	%xmm0, %xmm1
	movd	%xmm1, %eax
	ret

bitconverts can happen due to various calling conventions that require
fp values to passed in integer regs in some cases, e.g. when returning
a complex.

llvm-svn: 46414

llvm-svn: 46413

llvm-svn: 46411

llvm-svn: 46410

llvm-svn: 46409

This fixes PR1769.

llvm-svn: 46408