llvm-svn: 132108

llvm-svn: 132107

Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.

The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.

llvm-svn: 132106

rdar://problem/6920088

llvm-svn: 132105

Use a proper worklist for use-def traversal without holding onto an
iterator. Now that we process all IV uses, we need complete logic for
resusing existing derived IV defs. See HoistStep.

llvm-svn: 132103

This doesn't change functionality (much), but it allows for a more fine-grained
eviction policy. The current policy only compares spill weights, and that is not
always the best thing to do.  Spill weights are designed to serve linear scan,
and they don't consider live range splitting.

Add a mechanism so canEvict() can request that a live range be evicted and
split/spilled. This is to avoid infinite eviction loops.

llvm-svn: 132101

Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.

The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099

llvm-svn: 132098

llvm-svn: 132097

llvm-svn: 132087

llvm-svn: 132086

them.

I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.

llvm-svn: 132084

llvm-svn: 132083

Part of rdar://9119939

llvm-svn: 132081

been defined in MipsInstrFPU.td.

llvm-svn: 132076

llvm-svn: 132074

llvm-svn: 132073

llvm-svn: 132071

llvm-svn: 132070

return 0 if there are no function calls made. 

llvm-svn: 132065

llvm-svn: 132063

llvm-svn: 132062

MSVC doesn't support 64 bit enum. 
OpcodeMask is not used anywhere in the code base.

llvm-svn: 132057

buggy methods that parse these directives.

llvm-svn: 132045

llvm-svn: 132044

llvm-svn: 132043

fixes <rdar://problem/9495913>

llvm-svn: 132042

target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

llvm-svn: 132041

llvm-svn: 132040

reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039

cleanup and overdue test cases.

llvm-svn: 132038

one I found by inspection).

llvm-svn: 132037

LTO friendly as we can now correctly merge files compiled with or without
-fasynchronous-unwind-tables.

llvm-svn: 132033

llvm-svn: 132030

method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.

llvm-svn: 132028

Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026

llvm-svn: 132025

Part of rdar://9119939

llvm-svn: 132024

Part of rdar://9119939

llvm-svn: 132023

case of a switch instruction. Back off this optimization when this would
eliminate all of the predecessors to the latch.

Sorry, I am unable to reduce a reasonably sized test case.

rdar://9486843

llvm-svn: 132022