Commits · 49cadab3855b64a5116581efec6a53d027e932e8 · Roger Ferrer / llvm-epi-0.8

"git@repo.hca.bsc.es:rferrer/llvm-epi-0.8.git" did not exist on "ad58828354e97fdea2124eb02ffe1ae80e9e8b34"

Jun 17, 2006
- Implement the getPointerRegClass method, which is required for the ptr_rc · 49cadab3
  Chris Lattner authored Jun 17, 2006
```
magic to work.

llvm-svn: 28847
```
  49cadab3
May 04, 2006
- Move some methods out of MachineInstr into MachineOperand · 10d63416
  Chris Lattner authored May 04, 2006
```
llvm-svn: 28102
```
  10d63416
Mar 16, 2006
- teach the ppc backend how to spill/reload vector regs · 91400bd4
  Chris Lattner authored Mar 16, 2006
```
llvm-svn: 26806
```
  91400bd4
- Add support for copying registers. still needed: spilling and reloading them · fd9f3e8e
  Chris Lattner authored Mar 16, 2006
```
llvm-svn: 26800
```
  fd9f3e8e
Mar 06, 2006
- implement TII::insertNoop · ea79d9fd
  Chris Lattner authored Mar 05, 2006
```
llvm-svn: 26562
```
  ea79d9fd
Feb 02, 2006
- add 64b gpr store to the possible list of isStoreToStackSlot opcodes. · 4efb3289
  Nate Begeman authored Feb 02, 2006
```
llvm-svn: 25916
```
  4efb3289
- implement isStoreToStackSlot for PPC · c327d71e
  Chris Lattner authored Feb 02, 2006
```
llvm-svn: 25914
```
  c327d71e
- Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far... · bb53acd0
  Chris Lattner authored Feb 02, 2006
```
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place.  Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913
```
  bb53acd0
Oct 19, 2005
- teach ppc backend these are copies · 5f376232
  Chris Lattner authored Oct 19, 2005
```
llvm-svn: 23813
```
  5f376232
Oct 18, 2005
- First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is · 0b71e007
  Nate Begeman authored Oct 18, 2005
```
purely mechanical.

llvm-svn: 23778
```
  0b71e007
Oct 16, 2005
- More PPC32 -> PPC changes, as well as merging some classes that were · 6cca84e4
  Nate Begeman authored Oct 16, 2005
```
redundant after the change.

llvm-svn: 23759
```
  6cca84e4
Oct 15, 2005
- Rename PPC32*.h to PPC*.h · 6f3b9546
  Chris Lattner authored Oct 14, 2005
```
This completes the grand PPC file renaming

llvm-svn: 23745
```
  6f3b9546
- Rename PowerPC*.h to PPC*.h · bfca1ab7
  Chris Lattner authored Oct 14, 2005
```
llvm-svn: 23743
```
  bfca1ab7
- Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td · 0921e3bf
  Chris Lattner authored Oct 14, 2005
```
llvm-svn: 23738
```
  0921e3bf
Oct 07, 2005

Fix a CQ regression from my patch to split F32/F64 into seperate register · e3735922

Chris Lattner authored Oct 07, 2005

classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

llvm-svn: 23654

e3735922

Oct 01, 2005

Modify the ppc backend to use two register classes for FP: F8RC and F4RC. · d3eee1a0

Chris Lattner authored Oct 01, 2005

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577

d3eee1a0

Sep 09, 2005

Teach the code generator that rlwimi is commutable if the rotate amount · c37a2f13

Chris Lattner authored Sep 09, 2005

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

c37a2f13

Apr 22, 2005
- Remove trailing whitespace · b440243e
  Misha Brukman authored Apr 21, 2005
```
llvm-svn: 21425
```
  b440243e
Apr 12, 2005
- Initial support for allocation condition registers · f67f3bf6
  Nate Begeman authored Apr 12, 2005
```
llvm-svn: 21246
```
  f67f3bf6
Oct 08, 2004

Add ori reg, reg, 0 as a move instruction. This can be generated from · c6b63cd2

Nate Begeman authored Oct 07, 2004

loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr

llvm-svn: 16825

c6b63cd2

Aug 17, 2004
- PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC* · 116f9277
  Misha Brukman authored Aug 17, 2004
```
llvm-svn: 15850
```
  116f9277
Aug 12, 2004
- Set the is64bit flag and propagate it to PowerPCRegisterInfo · aea37d65
  Misha Brukman authored Aug 11, 2004
```
llvm-svn: 15671
```
  aea37d65
Aug 11, 2004
- Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets · dad438bf
  Misha Brukman authored Aug 10, 2004
```
llvm-svn: 15631
```
  dad438bf
Jul 26, 2004
- ADDI can take several forms, including: · 58499ead
  Misha Brukman authored Jul 26, 2004
```
  addi r1, r2, 0
  addi r1, <frame index #n>, 0

so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.

llvm-svn: 15244
```
  58499ead
- assert() on MachineInstr properties instead of checking them dynamically · 6c125a92
  Misha Brukman authored Jul 26, 2004
```
llvm-svn: 15243
```
  6c125a92
- * Recognize `addi r1, r2, 0' a move instruction · 43f1c404
  Misha Brukman authored Jul 26, 2004
```
* List formats of instructions currently recognized as moves

llvm-svn: 15242
```
  43f1c404
Jul 16, 2004
- Fix code formatting · 780da842
  Misha Brukman authored Jul 16, 2004
```
llvm-svn: 14899
```
  780da842
- Implement PowerPCInstrInfo::isMoveInstr(), patch by Nate Begeman · 3adf84ba
  Misha Brukman authored Jul 16, 2004
```
llvm-svn: 14898
```
  3adf84ba
Jun 21, 2004
- Initial revision · e05203fb
  Misha Brukman authored Jun 21, 2004
```
llvm-svn: 14283
```
  e05203fb
Feb 29, 2004
- Adjust to change in TII ctor arguments · ed01da8f
  Chris Lattner authored Feb 29, 2004
```
llvm-svn: 11987
```
  ed01da8f
- These two virtual methods are never called. · ca89812d
  Chris Lattner authored Feb 29, 2004
```
llvm-svn: 11984
```
  ca89812d
Feb 25, 2004
- SparcV8 skeleton · 9a5bd7fc
  Brian Gaeke authored Feb 25, 2004
```
llvm-svn: 11828
```
  9a5bd7fc