llvm-svn: 104412

llvm-svn: 104411

llvm-svn: 104410

Evan please verify!

llvm-svn: 104408

llvm-svn: 104404

llvm-svn: 104396

llvm-svn: 104394

llvm-svn: 104392

llvm-svn: 104391

Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.

llvm-svn: 104385

llvm-svn: 104381

so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380

that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377

reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372

llvm-svn: 104338

llvm-svn: 104337

Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336

If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

llvm-svn: 104334

pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333

llvm-svn: 104331

llvm-svn: 104330

eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328

llvm-svn: 104326

llvm-svn: 104325

This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323

This correctly handles partial redefines and undef uses.

llvm-svn: 104322

definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321

<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320

isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318

differently. This will make adding ELF support easier in the long run.

llvm-svn: 104317

llvm-svn: 104316

llvm-svn: 104311

tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308

Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).

llvm-svn: 104307

llvm-svn: 104306

llvm-svn: 104303

llvm-svn: 104302

llvm-svn: 104300

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

llvm-svn: 104293

llvm-svn: 104290