llvm-svn: 100669

llvm-svn: 100667

llvm-svn: 100666

llvm-svn: 100665

llvm-svn: 100664

llvm-svn: 100663

llvm-svn: 100660

llvm-svn: 100659

llvm-svn: 100658

llvm-svn: 100657

llvm-svn: 100655

VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.

llvm-svn: 100652

llvm-svn: 100651

Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(

llvm-svn: 100650

llvm-svn: 100648

llvm-svn: 100647

Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.

llvm-svn: 100646

llvm-svn: 100643

llvm-svn: 89672

llvm-svn: 89218

llvm-svn: 82788

llvm-svn: 82657

llvm-svn: 82483

llvm-svn: 79436

llvm-svn: 79084

llvm-svn: 78908

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78736

llvm-svn: 78564

llvm-svn: 76612

Latency information for ARM v6. It's rough and not yet hooked up. Right now  we are only using branch latency to determine if-conversion limits.

llvm-svn: 73747