addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957

llvm-svn: 95949

llvm-svn: 95440

llvm-svn: 95410

llvm-svn: 95408

TSFlags directly instead of a TargetInstrDesc.

llvm-svn: 95405

instructions with no operands.  It can now handle

define void @test2() nounwind { ret void }

llvm-svn: 95261

llvm-svn: 94147

Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.

llvm-svn: 93278

instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.

llvm-svn: 93210

llvm-svn: 91104

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.

llvm-svn: 90608

for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144

it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.

llvm-svn: 89865

- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745

Fix a bootstrap failure.

Provide special isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE
interfaces to explicitly request checking for post-frame ptr elimination
operands.  This uses a heuristic so it isn't reliable for correctness.

llvm-svn: 87047

Add hasLoadFromStackSlot and hasStoreToStackSlot to return whether a
machine instruction loads or stores from/to a stack slot.  Unlike
isLoadFromStackSlot and isStoreFromStackSlot, the instruction may be
something other than a pure load/store (e.g. it may be an arithmetic
operation with a memory operand).  This helps AsmPrinter determine when
to print a spill/reload comment.

This is only a hint since we may not be able to figure this out in all
cases.  As such, it should not be relied upon for correctness.

Implement for X86.  Return false by default for other architectures.

llvm-svn: 87026

unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622

MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.

llvm-svn: 83696

information when unfolding memory references.

llvm-svn: 83656

implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475

they make it less convenient to add new entries.

llvm-svn: 83308

It's not legal to fold a load from a narrower stack slot into a wider instruction. If done, the instruction does a 64-bit load and that's not
safe. This can happen we a subreg_to_reg 0 has been coalesced. One
exception is when the instruction that folds the load is a move, then we
can simply turn it into a 32-bit load from the stack slot.                                                                                                                    

rdar://7170444

llvm-svn: 81494

Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.

llvm-svn: 80904

bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508

Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900

llvm-svn: 75749

llvm-svn: 75290

llvm-svn: 75266

PIC-base to be added in.

llvm-svn: 75238

llvm-svn: 75236

MachineOperand is a reference to a stub, not a reference to the
global variable itself.  Look no context needed!

llvm-svn: 75233

isel.

llvm-svn: 75117

llvm-svn: 75107

llvm-svn: 75086

llvm-svn: 74327