Commits · 4b0986b6c171390559c618da6d40dad14040d637 · Roger Ferrer / llvm-epi-0.8

Oct 13, 2010
- Start handling more global variables. · dd0821e7
  Eric Christopher authored Oct 13, 2010
```
llvm-svn: 116401
```
  dd0821e7
- Limit load / store issues (at least until we have a true multi-issue aware scheduler). · 39121589
  Evan Cheng authored Oct 13, 2010
```
llvm-svn: 116389
```
  39121589
- Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test · 6e27b4f5
  Bill Wendling authored Oct 13, 2010
```
just yet.

llvm-svn: 116386
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  6e27b4f5
- Add encodings for VCVT instructions. · 576fd0b1
  Bill Wendling authored Oct 13, 2010
```
llvm-svn: 116385
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  576fd0b1
- Add ARM encoding information for comparisons, forced-cc-out arithmetics, and · 8c519c0d
  Jim Grosbach authored Oct 13, 2010
```
arithmetic-with-carry-in instructions.

llvm-svn: 116384
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  8c519c0d
- Add VCMPZ and VABS. · da4ddf0f
  Bill Wendling authored Oct 13, 2010
```
llvm-svn: 116383
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  da4ddf0f
- Refactor VCMP instructions. · f9ca5354
  Bill Wendling authored Oct 13, 2010
```
llvm-svn: 116379
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  f9ca5354
- Add the rest of the ARM so_reg encoding options (register shifted register) · efd53697
  Jim Grosbach authored Oct 12, 2010
```
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377
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  efd53697
- Add encodings for VNMUL[SD]. · 7dd8c0b9
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116375
```
  7dd8c0b9
- Add encodings for VDIV and VMUL. · a06aee82
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116370
```
  a06aee82
- Turn some fp stackifier assertion into errors to avoid silently generating bad... · d565b44a
  Evan Cheng authored Oct 12, 2010
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Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

llvm-svn: 116368
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  d565b44a
- Move the ARM so_imm encoding into a custom operand encoder and remove the · 12e493ac
  Jim Grosbach authored Oct 12, 2010
```
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
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  12e493ac
- Refactor some of the encoding logic into a base class. This keeps us from having · 42200bca
  Bill Wendling authored Oct 12, 2010
```
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
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  42200bca
- Add custom encoder for the 's' bit denoting whether an ARM arithmetic · d9d31daf
  Jim Grosbach authored Oct 12, 2010
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
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  d9d31daf
- Add encoding for VSUB and VCMP. · 646a5067
  Bill Wendling authored Oct 12, 2010
```
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
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  646a5067
- Encoding for VADDD. Plus a test for the VFP instructions. · ac6cd007
  Bill Wendling authored Oct 12, 2010
```
llvm-svn: 116348
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  ac6cd007
- Split out the "size" field from the encoding. The newer documentation has it as · 98c29d73
  Bill Wendling authored Oct 12, 2010
```
a separate bit in the coding.

llvm-svn: 116347
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  98c29d73
Oct 12, 2010
- Fix thinko in arm fast isel alloca rewrite. · 22e051ee
  Eric Christopher authored Oct 12, 2010
```
llvm-svn: 116339
```
  22e051ee
- Encoding for ARM-mode VADD.F32 instruction. · 576640f0
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116338
```
  576640f0
- Combine these together - should probably have some text associated · 604e1428
  Eric Christopher authored Oct 12, 2010
```
that says what why what we just asserted is wrong.

llvm-svn: 116333
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  604e1428
- Mark variable 'NoImplicitFloatOps' used only in an assert as used. · eb7b91d4
  Nick Lewycky authored Oct 12, 2010
```
llvm-svn: 116323
```
  eb7b91d4
- Add MOVi ARM encoding. · 0e57a9f7
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116321
```
  0e57a9f7
- Initial va_arg support for x86-64. Patch by David Meyer! · 395a898b
  Dan Gohman authored Oct 12, 2010
```
llvm-svn: 116319
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  395a898b
- Nuke unused wrapper function. · feeae27a
  Jim Grosbach authored Oct 12, 2010
```
llvm-svn: 116318
```
  feeae27a
- Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. · aec74532
  Jakob Stoklund Olesen authored Oct 12, 2010
```
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
```
  aec74532
- Add encoding information for the remainder of the generic arithmetic · 6fead930
  Jim Grosbach authored Oct 12, 2010
```
ARM instructions.

llvm-svn: 116313
```
  6fead930
- PR8359: The ARM backend may end up allocating registers D16 to D31 when · dd6eb5b5
  Bob Wilson authored Oct 12, 2010
```
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310
```
  dd6eb5b5
- Rework alloca handling so that we can load or store from casted · 7cd5cda6
  Eric Christopher authored Oct 12, 2010
```
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
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  7cd5cda6
- Handle a wider arrangement of loads. · db3bcc99
  Eric Christopher authored Oct 12, 2010
```
llvm-svn: 116284
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  db3bcc99
- More ARM scheduling itinerary fixes. · e790afcb
  Evan Cheng authored Oct 11, 2010
```
llvm-svn: 116266
```
  e790afcb
- MC machine encoding for simple aritmetic instructions that use a shifted · b7c2962d
  Jim Grosbach authored Oct 11, 2010
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register operand.

llvm-svn: 116259
```
  b7c2962d
- Second set of ARM/MC/ELF changes. · 109ff296
  Jason W Kim authored Oct 11, 2010
```
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
```
  109ff296
- Proper VST scheduling itineraries. · 94ad008b
  Evan Cheng authored Oct 11, 2010
```
llvm-svn: 116251
```
  94ad008b
- Use a sane mechanism for that assert. · d42340ec
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116249
```
  d42340ec
Oct 11, 2010
- We're not going to handle dynamic allocas anywhere else. · 72b91c17
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116240
```
  72b91c17
- Make sure that the call stack adjustments have default operands. Also · 71ef1af6
  Eric Christopher authored Oct 11, 2010
```
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
```
  71ef1af6
- PowerPC varargs functions store live-in registers on the stack. Make sure we use · 6c4353ec
  Jakob Stoklund Olesen authored Oct 11, 2010
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virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

llvm-svn: 116222
```
  6c4353ec
- Found a bug turning this on by default. Disable again for now. · e2a0b684
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116220
```
  e2a0b684
- Fix help text. · 46cc854e
  Eric Christopher authored Oct 11, 2010
```
llvm-svn: 116218
```
  46cc854e
- Change flag from Enable to Disable since we're enabled by default. · 5501b7e8
  Eric Christopher authored Oct 11, 2010
```
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
```
  5501b7e8