llvm-svn: 101964

CodeGen's ComputeMaskedBits was being over-conservative when computing
bits for an ADD.

llvm-svn: 101963

llvm-svn: 101962

llvm-svn: 101960

(shl (or x,c), 3) the same as (shl (add x, c), 3)
when x doesn't have any bits from c set.

This finishes off PR1135.  Before we compiled the block to:
to:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	leaq	2(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	leaq	1(%rdx), %r9
	movl	%esi, (%rdi,%r9,4)
	addq	$3, %rdx
	movl	%esi, (%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

Now we produce:

LBB0_3:                                 ## %bb
	cmpb	$4, %dl
	sete	%dl
	addb	%dl, %cl
	movb	%cl, %dl
	shlb	$2, %dl
	addb	%r8b, %dl
	shlb	$2, %dl
	movzbl	%dl, %edx
	movl	%esi, (%rdi,%rdx,4)
	movl	%esi, 8(%rdi,%rdx,4)
	movl	%esi, 4(%rdi,%rdx,4)
	movl	%esi, 12(%rdi,%rdx,4)
	incb	%r8b
	decb	%al
	movb	%r8b, %dl
	jne	LBB0_1

llvm-svn: 101958

Fix USRs for @synthesize.
Add more USR tests.

llvm-svn: 101954

llvm-svn: 101953

llvm-svn: 101952

user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own.  This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)

llvm-svn: 101951

Rename ValueMapTy as ValueToValueMapTy to clearly indicate that this has no replationship with ADT/ValueMap.

llvm-svn: 101950

llvm-svn: 101949

It is ok to have c++-ness inside extern "C" 
block. Fixes pr6644.

llvm-svn: 101948

llvm-svn: 101943

instead of just asserting.

llvm-svn: 101942

llvm-svn: 101941

a const_cast.

llvm-svn: 101940

into ContentCache::getBuffer.  This allows it to produce 
diagnostics on the broken #include line instead of without a 
location.

llvm-svn: 101939

objective-c methods. Fixes radar 7875968.

llvm-svn: 101935

after the llvm-2.7 release.

llvm-svn: 101934

register is not killed in the loop.

This fixes 188.ammp on ARM where the post-ra scheduler would grab a register
that looked available but wasn't.

A testcase would be huge and fragile, sorry.

llvm-svn: 101930

as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929

reduce.

llvm-svn: 101925

about it instead of producing tons of garbage from the lexer.

It would be even better for sourcemgr to dynamically transcode (e.g.
from UTF16 -> UTF8).

llvm-svn: 101924

llvm-svn: 101921

llvm-svn: 101920

matches how we currently handle structs, and this correctly handles
-fno-bitfield-type-align.

llvm-svn: 101918

transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915

llvm-svn: 101914

llvm-svn: 101913

llvm-svn: 101912

Fix a bug which triggered the assertion I added yesterday. Basically, when we initialize the vtable pointer for a virtual base, and there was another path from the most derived class to another base with the same class type, we would use the wrong base.

llvm-svn: 101911

llvm-svn: 101909

@encode expression. 

llvm-svn: 101907

into SelectionDAGBuilder. This avoids a separate pass over the
instructions, and has the side effect of providing debug location
information to the copy.

llvm-svn: 101906

they end up doing nothing.

llvm-svn: 101904

llvm-svn: 101903

llvm-svn: 101902

llvm-svn: 101901

llvm-svn: 101900

llvm-svn: 101899