llvm-svn: 11818

into a single LEA instruction.  This should improve the code generated for
things like X->A.B.C[12].D.

The bigger benefit is still coming though.  Note that this uses an LEA instruction
instead of an add, giving the register allocator more freedom.  We should probably
never generate ADDri32's.

llvm-svn: 11817

an intermediate register.

llvm-svn: 11816

llvm-svn: 11813

llvm-svn: 11811

Also fix problem where we didn't check to see if a node pointer was null.
Though fclose(null) doesn't make a lot of sense, 300.twolf does it.

llvm-svn: 11810

llvm-svn: 11804

longer was getting this #include, it always fell back on the less precise
floating point initializer values, causing some testsuite failures.

llvm-svn: 11803

llvm-svn: 11801

llvm-svn: 11799

allocator.

The implementation is completely rewritten and now employs several
optimizations not exercised before. For example for 164.gzip we have
997 loads and 699 stores vs the 1221 loads and 880 stores we have
before.

llvm-svn: 11798

This case occurs many times in various benchmarks, especially when combined
with the previous patch.  This allows it to get stuff like:
  if (X == 4 || X == 3)
    if (X == 5 || X == 8)

and

switch (X) {
case 4: case 5: case 6:
  if (X == 4 || X == 5)

llvm-svn: 11797

register mapping or a stack slot mapping.

llvm-svn: 11795

llvm-svn: 11793

This turns code like this:
  if (X == 4 | X == 7)
and
  if (X != 4 & X != 7)
into switch instructions.

llvm-svn: 11792

llvm-svn: 11782

llvm-svn: 11781

251 (providing a generic machine code rewriter/spiller).

llvm-svn: 11780

llvm-svn: 11775

llvm-svn: 11774

Also, turn 'shr int %X, 1234' into 'shr int %X, 31'

llvm-svn: 11768

llvm-svn: 11759

llvm-svn: 11758

llvm-svn: 11757

llvm-svn: 11756

llvm-svn: 11755

block into MachineBasicBlock::getFirstTerminator().

This also fixes a bug in the implementation of the above in both
RegAllocLocal and InstrSched, where instructions where added after the
terminator if the basic block's only instruction was a terminator (it
shouldn't matter for RegAllocLocal since this case never occurs in
practice).

llvm-svn: 11748

block we are in might be empty

llvm-svn: 11744

eventually get an assignment due to elimination of PHIs.

llvm-svn: 11743

llvm-svn: 11742

whether this is the sign bit or not, so check unsigned comparisons as well.

llvm-svn: 11740

Improved PhysRegTracker interface. RegAlloc lazily allocates the register tracker using a std::auto_ptr

llvm-svn: 11738

llvm-svn: 11737

llvm-svn: 11735

with "predication"

llvm-svn: 11734

Simplify iterator usage now that we have next(). Also don't pass iterators by reference now that MachineInstr* are in an ilist

llvm-svn: 11732

llvm-svn: 11729

llvm-svn: 11728

Implement cast Type::ULongTy -> double

llvm-svn: 11726

llvm-svn: 11724